* [PATCH v2] board: Add support for iMX8QXP AI_ML board
@ 2020-07-29 5:05 Manivannan Sadhasivam
2020-08-03 15:03 ` Stefano Babic
0 siblings, 1 reply; 4+ messages in thread
From: Manivannan Sadhasivam @ 2020-07-29 5:05 UTC (permalink / raw)
To: u-boot
This commit adds initial board support for iMX8QXP AI_ML board from
Einfochips. This board is one of the 96Boards Consumer Edition and AI
boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale.
This initial supports contains following peripherals which are tested and
known to work:
1. Debug serial via UART2
2. SD card
3. Ethernet
More information about this board can be found in arrow website:
https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v2:
* Rebased onto u-boot/master and fixed one build issue
* Added review from Fabio
arch/arm/mach-imx/imx8/Kconfig | 6 ++
board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++
board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++
board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++
board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++
.../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++
board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++
board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++
configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++
include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++
10 files changed, 409 insertions(+)
create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig
create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS
create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile
create mode 100644 board/einfochips/imx8qxp_ai_ml/README
create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg
create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c
create mode 100644 configs/imx8qxp_ai_ml_defconfig
create mode 100644 include/configs/imx8qxp_ai_ml.h
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9d1f73dfc7..308122d62a 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -75,6 +75,11 @@ config TARGET_GIEDI
select BOARD_LATE_INIT
select IMX8QXP
+config TARGET_IMX8QXP_AI_ML
+ bool "Support i.MX8QXP AI_ML board"
+ select BOARD_EARLY_INIT_F
+ select IMX8QXP
+
config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
@@ -93,6 +98,7 @@ config TARGET_IMX8QXP_MEK
endchoice
+source "board/einfochips/imx8qxp_ai_ml/Kconfig"
source "board/freescale/imx8qm_mek/Kconfig"
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig
new file mode 100644
index 0000000000..b6806b8859
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_IMX8QXP_AI_ML
+
+config SYS_BOARD
+ default "imx8qxp_ai_ml"
+
+config SYS_VENDOR
+ default "einfochips"
+
+config SYS_CONFIG_NAME
+ default "imx8qxp_ai_ml"
+
+config SYS_MALLOC_LEN
+ default 0x2400000
+
+config ENV_SIZE
+ default 0x1000
+
+config ENV_OFFSET
+ default 0x400000
+
+endif
diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
new file mode 100644
index 0000000000..add0bd9431
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QXP AI_ML BOARD
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: board/einfochips/imx8qxp_ai_ml/
+F: include/configs/imx8qxp_ai_ml.h
+F: configs/imx8qxp_ai_ml_defconfig
diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile
new file mode 100644
index 0000000000..e08774dc6e
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2019 Linaro Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8qxp_ai_ml.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README
new file mode 100644
index 0000000000..488920580f
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/README
@@ -0,0 +1,49 @@
+U-Boot for the Einfochips i.MX8QXP AI_ML board
+
+Quick Start
+===========
+
+- Get and Build the ARM Trusted firmware
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf/
+$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
+$ make PLAT=imx8qxp bl31
+
+Get scfw_tcm.bin and ahab-container.img
+=======================================
+
+$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml-scfw-tcm.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin
+$ chmod +x firmware-imx-8.1.bin
+$ ./firmware-imx-8.1.bin
+
+Copy the following binaries to U-Boot folder:
+
+$ cp imx-atf/build/imx8qxp/release/bl31.bin .
+$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img .
+
+Build U-Boot
+============
+
+$ make imx8qxp_ai_ml_defconfig
+$ make u-boot-dtb.imx
+
+Flash the binary into the SD card
+=================================
+
+Burn the u-boot-dtb.imx binary to SD card offset 32KB:
+
+$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
+
+Boot
+====
+
+Set Boot switch SW2: 1100.
diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
new file mode 100644
index 0000000000..7ba014ac07
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2019 Linaro Ltd.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ sc_pm_clock_rate_t rate = SC_80MHZ;
+ int ret;
+
+ /* Set UART2 clock root to 80 MHz */
+ ret = sc_pm_setup_uart(SC_R_UART_2, rate);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: iMX8QXP AI_ML\n");
+
+ build_info();
+ print_bootinfo();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+/* Board specific reset that is system reset */
+
+void reset_cpu(ulong addr)
+{
+ /* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+#endif
diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
new file mode 100644
index 0000000000..4fc5ade313
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-aiml-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c
new file mode 100644
index 0000000000..2e6e0741e5
--- /dev/null
+++ b/board/einfochips/imx8qxp_ai_ml/spl.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2019 Linaro Ltd.
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ arch_cpu_init();
+
+ timer_init();
+
+ preloader_console_init();
+
+ puts("Normal Boot\n");
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig
new file mode 100644
index 0000000000..e20a0c783e
--- /dev/null
+++ b/configs/imx8qxp_ai_ml_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_IMX8QXP_AI_ML=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_FAT_WRITE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h
new file mode 100644
index 0000000000..bdac710103
--- /dev/null
+++ b/include/configs/imx8qxp_ai_ml.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Copyright 2019 Linaro Ltd.
+ */
+
+#ifndef __IMX8QXP_AI_ML_H
+#define __IMX8QXP_AI_ML_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
+#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x013E000
+#define CONFIG_SPL_BSS_START_ADDR 0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE 0x5a080000
+#define CONFIG_MALLOC_F_ADDR 0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_SEPARATE
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttyLP2 earlycon\0" \
+ "fdt_addr_r=0x83000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "ramdisk_addr_r=0x94400000\0" \
+ "scriptaddr=0x89000000\0" \
+ "fdtfile=imx8qxp-ai_ml.dtb\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "image=Image\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
+ "\0" \
+ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+ "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
+ BOOTENV
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+
+/* USDHC2 is the SD card interface */
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_2 0x880000000
+#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QXP_AI_ML_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2] board: Add support for iMX8QXP AI_ML board
2020-07-29 5:05 [PATCH v2] board: Add support for iMX8QXP AI_ML board Manivannan Sadhasivam
@ 2020-08-03 15:03 ` Stefano Babic
2020-08-03 15:05 ` Stefano Babic
0 siblings, 1 reply; 4+ messages in thread
From: Stefano Babic @ 2020-08-03 15:03 UTC (permalink / raw)
To: u-boot
Hi Mani,
On 29.07.20 07:05, Manivannan Sadhasivam wrote:
> This commit adds initial board support for iMX8QXP AI_ML board from
> Einfochips. This board is one of the 96Boards Consumer Edition and AI
> boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale.
>
> This initial supports contains following peripherals which are tested and
> known to work:
>
> 1. Debug serial via UART2
> 2. SD card
> 3. Ethernet
>
> More information about this board can be found in arrow website:
> https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools
>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>
I see several errors when building this board
https://travis-ci.org/github/sbabic/u-boot-imx/jobs/714193236
Anyway, where is the DTS for this board ?
Best regards,
Stefano Babic
> Changes in v2:
>
> * Rebased onto u-boot/master and fixed one build issue
> * Added review from Fabio
>
> arch/arm/mach-imx/imx8/Kconfig | 6 ++
> board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++
> board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++
> board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++
> board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++
> .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++
> board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++
> board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++
> configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++
> include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++
> 10 files changed, 409 insertions(+)
> create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig
> create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS
> create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile
> create mode 100644 board/einfochips/imx8qxp_ai_ml/README
> create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
> create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg
> create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c
> create mode 100644 configs/imx8qxp_ai_ml_defconfig
> create mode 100644 include/configs/imx8qxp_ai_ml.h
>
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index 9d1f73dfc7..308122d62a 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -75,6 +75,11 @@ config TARGET_GIEDI
> select BOARD_LATE_INIT
> select IMX8QXP
>
> +config TARGET_IMX8QXP_AI_ML
> + bool "Support i.MX8QXP AI_ML board"
> + select BOARD_EARLY_INIT_F
> + select IMX8QXP
> +
> config TARGET_IMX8QM_MEK
> bool "Support i.MX8QM MEK board"
> select BOARD_LATE_INIT
> @@ -93,6 +98,7 @@ config TARGET_IMX8QXP_MEK
>
> endchoice
>
> +source "board/einfochips/imx8qxp_ai_ml/Kconfig"
> source "board/freescale/imx8qm_mek/Kconfig"
> source "board/freescale/imx8qxp_mek/Kconfig"
> source "board/advantech/imx8qm_rom7720_a1/Kconfig"
> diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig
> new file mode 100644
> index 0000000000..b6806b8859
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/Kconfig
> @@ -0,0 +1,21 @@
> +if TARGET_IMX8QXP_AI_ML
> +
> +config SYS_BOARD
> + default "imx8qxp_ai_ml"
> +
> +config SYS_VENDOR
> + default "einfochips"
> +
> +config SYS_CONFIG_NAME
> + default "imx8qxp_ai_ml"
> +
> +config SYS_MALLOC_LEN
> + default 0x2400000
> +
> +config ENV_SIZE
> + default 0x1000
> +
> +config ENV_OFFSET
> + default 0x400000
> +
> +endif
> diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
> new file mode 100644
> index 0000000000..add0bd9431
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8QXP AI_ML BOARD
> +M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +S: Maintained
> +F: board/einfochips/imx8qxp_ai_ml/
> +F: include/configs/imx8qxp_ai_ml.h
> +F: configs/imx8qxp_ai_ml_defconfig
> diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile
> new file mode 100644
> index 0000000000..e08774dc6e
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright 2019 Linaro Ltd.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += imx8qxp_ai_ml.o
> +obj-$(CONFIG_SPL_BUILD) += spl.o
> diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README
> new file mode 100644
> index 0000000000..488920580f
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/README
> @@ -0,0 +1,49 @@
> +U-Boot for the Einfochips i.MX8QXP AI_ML board
> +
> +Quick Start
> +===========
> +
> +- Get and Build the ARM Trusted firmware
> +- Get scfw_tcm.bin and ahab-container.img
> +- Build U-Boot
> +- Flash the binary into the SD card
> +- Boot
> +
> +Get and Build the ARM Trusted firmware
> +======================================
> +
> +$ git clone https://source.codeaurora.org/external/imx/imx-atf
> +$ cd imx-atf/
> +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
> +$ make PLAT=imx8qxp bl31
> +
> +Get scfw_tcm.bin and ahab-container.img
> +=======================================
> +
> +$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml-scfw-tcm.bin
> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin
> +$ chmod +x firmware-imx-8.1.bin
> +$ ./firmware-imx-8.1.bin
> +
> +Copy the following binaries to U-Boot folder:
> +
> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
> +$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img .
> +
> +Build U-Boot
> +============
> +
> +$ make imx8qxp_ai_ml_defconfig
> +$ make u-boot-dtb.imx
> +
> +Flash the binary into the SD card
> +=================================
> +
> +Burn the u-boot-dtb.imx binary to SD card offset 32KB:
> +
> +$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
> +
> +Boot
> +====
> +
> +Set Boot switch SW2: 1100.
> diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
> new file mode 100644
> index 0000000000..7ba014ac07
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
> @@ -0,0 +1,78 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Copyright 2019 Linaro Ltd.
> + */
> +
> +#include <common.h>
> +#include <errno.h>
> +#include <linux/libfdt.h>
> +#include <fsl_esdhc.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sci/sci.h>
> +#include <asm/arch/imx8-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_early_init_f(void)
> +{
> + sc_pm_clock_rate_t rate = SC_80MHZ;
> + int ret;
> +
> + /* Set UART2 clock root to 80 MHz */
> + ret = sc_pm_setup_uart(SC_R_UART_2, rate);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +#if IS_ENABLED(CONFIG_FEC_MXC)
> +#include <miiphy.h>
> +
> +int board_phy_config(struct phy_device *phydev)
> +{
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +
> + if (phydev->drv->config)
> + phydev->drv->config(phydev);
> +
> + return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> + puts("Board: iMX8QXP AI_ML\n");
> +
> + build_info();
> + print_bootinfo();
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + return 0;
> +}
> +
> +/* Board specific reset that is system reset */
> +
> +void reset_cpu(ulong addr)
> +{
> + /* TODO */
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, struct bd_info *bd)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
> new file mode 100644
> index 0000000000..4fc5ade313
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + *
> + * Refer doc/README.imx8image for more details about how-to configure
> + * and create imx8image boot image
> + */
> +
> +#define __ASSEMBLY__
> +
> +/* Boot from SD, sector size 0x400 */
> +BOOT_FROM SD 0x400
> +/* SoC type IMX8QX */
> +SOC_TYPE IMX8QX
> +/* Append seco container image */
> +APPEND mx8qx-ahab-container.img
> +/* Create the 2nd container */
> +CONTAINER
> +/* Add scfw image with exec attribute */
> +IMAGE SCU mx8qx-aiml-scfw-tcm.bin
> +/* Add ATF image with exec attribute */
> +IMAGE A35 bl31.bin 0x80000000
> +/* Add U-Boot image with load attribute */
> +DATA A35 u-boot-dtb.bin 0x80020000
> diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c
> new file mode 100644
> index 0000000000..2e6e0741e5
> --- /dev/null
> +++ b/board/einfochips/imx8qxp_ai_ml/spl.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Copyright 2019 Linaro Ltd.
> + *
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <spl.h>
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void spl_board_init(void)
> +{
> + arch_cpu_init();
> +
> + timer_init();
> +
> + preloader_console_init();
> +
> + puts("Normal Boot\n");
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Clear global data */
> + memset((void *)gd, 0, sizeof(gd_t));
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig
> new file mode 100644
> index 0000000000..e20a0c783e
> --- /dev/null
> +++ b/configs/imx8qxp_ai_ml_defconfig
> @@ -0,0 +1,83 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8=y
> +CONFIG_SYS_TEXT_BASE=0x80020000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x4000
> +CONFIG_TARGET_IMX8QXP_AI_ML=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=4
> +CONFIG_SPL=y
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg"
> +CONFIG_BOOTDELAY=3
> +CONFIG_LOG=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_POWER_DOMAIN=y
> +CONFIG_SPL_WATCHDOG_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_CPU=y
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_DM=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_FAT_WRITE=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK=y
> +CONFIG_CLK_IMX8=y
> +CONFIG_CPU=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_IMX_LPI2C=y
> +CONFIG_MISC=y
> +CONFIG_DM_MMC=y
> +CONFIG_FSL_ESDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ADDR_ENABLE=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC_SHARE_MDIO=y
> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_FSL_LPUART=y
> +CONFIG_SPL_TINY_MEMSET=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h
> new file mode 100644
> index 0000000000..bdac710103
> --- /dev/null
> +++ b/include/configs/imx8qxp_ai_ml.h
> @@ -0,0 +1,95 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + * Copyright 2019 Linaro Ltd.
> + */
> +
> +#ifndef __IMX8QXP_AI_ML_H
> +#define __IMX8QXP_AI_ML_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
> +#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K)
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
> +
> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK 0x013E000
> +#define CONFIG_SPL_BSS_START_ADDR 0x00128000
> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
> +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000
> +#define CONFIG_MALLOC_F_ADDR 0x00120000
> +
> +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
> +
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#define CONFIG_OF_SEPARATE
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +/* Flat Device Tree Definitions */
> +#define CONFIG_OF_BOARD_SETUP
> +
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 1) \
> + func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "console=ttyLP2 earlycon\0" \
> + "fdt_addr_r=0x83000000\0" \
> + "kernel_addr_r=0x81000000\0" \
> + "ramdisk_addr_r=0x94400000\0" \
> + "scriptaddr=0x89000000\0" \
> + "fdtfile=imx8qxp-ai_ml.dtb\0" \
> + "fdt_high=0xffffffffffffffff\0" \
> + "image=Image\0" \
> + "initrd_addr=0x83800000\0" \
> + "initrd_high=0xffffffffffffffff\0" \
> + "netargs=setenv bootargs console=${console},${baudrate} " \
> + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
> + "\0" \
> + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
> + "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
> + BOOTENV
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR 0x80280000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
> +
> +/* USDHC2 is the SD card interface */
> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#define PHYS_SDRAM_1 0x80000000
> +#define PHYS_SDRAM_2 0x880000000
> +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
> +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
> +
> +/* Generic Timer Definitions */
> +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
> +
> +/* Networking */
> +#define CONFIG_FEC_XCV_TYPE RGMII
> +#define FEC_QUIRK_ENET_MAC
> +
> +#endif /* __IMX8QXP_AI_ML_H */
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] board: Add support for iMX8QXP AI_ML board
2020-08-03 15:03 ` Stefano Babic
@ 2020-08-03 15:05 ` Stefano Babic
2020-08-03 15:10 ` Stefano Babic
0 siblings, 1 reply; 4+ messages in thread
From: Stefano Babic @ 2020-08-03 15:05 UTC (permalink / raw)
To: u-boot
On 03.08.20 17:03, Stefano Babic wrote:
> Hi Mani,
>
> On 29.07.20 07:05, Manivannan Sadhasivam wrote:
>> This commit adds initial board support for iMX8QXP AI_ML board from
>> Einfochips. This board is one of the 96Boards Consumer Edition and AI
>> boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale.
>>
>> This initial supports contains following peripherals which are tested and
>> known to work:
>>
>> 1. Debug serial via UART2
>> 2. SD card
>> 3. Ethernet
>>
>> More information about this board can be found in arrow website:
>> https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools
>>
>> Reviewed-by: Peng Fan <peng.fan@nxp.com>
>> Reviewed-by: Fabio Estevam <festevam@gmail.com>
>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> ---
>>
>
> I see several errors when building this board
> https://travis-ci.org/github/sbabic/u-boot-imx/jobs/714193236
>
> Anyway, where is the DTS for this board ?
>
It seems I picked up the wrong version, I check it again..
Best regards,
Stefano Babic
>
>> Changes in v2:
>>
>> * Rebased onto u-boot/master and fixed one build issue
>> * Added review from Fabio
>>
>> arch/arm/mach-imx/imx8/Kconfig | 6 ++
>> board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++
>> board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++
>> board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++
>> board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++
>> .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++
>> board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++
>> board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++
>> configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++
>> include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++
>> 10 files changed, 409 insertions(+)
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/README
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg
>> create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c
>> create mode 100644 configs/imx8qxp_ai_ml_defconfig
>> create mode 100644 include/configs/imx8qxp_ai_ml.h
>>
>> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
>> index 9d1f73dfc7..308122d62a 100644
>> --- a/arch/arm/mach-imx/imx8/Kconfig
>> +++ b/arch/arm/mach-imx/imx8/Kconfig
>> @@ -75,6 +75,11 @@ config TARGET_GIEDI
>> select BOARD_LATE_INIT
>> select IMX8QXP
>>
>> +config TARGET_IMX8QXP_AI_ML
>> + bool "Support i.MX8QXP AI_ML board"
>> + select BOARD_EARLY_INIT_F
>> + select IMX8QXP
>> +
>> config TARGET_IMX8QM_MEK
>> bool "Support i.MX8QM MEK board"
>> select BOARD_LATE_INIT
>> @@ -93,6 +98,7 @@ config TARGET_IMX8QXP_MEK
>>
>> endchoice
>>
>> +source "board/einfochips/imx8qxp_ai_ml/Kconfig"
>> source "board/freescale/imx8qm_mek/Kconfig"
>> source "board/freescale/imx8qxp_mek/Kconfig"
>> source "board/advantech/imx8qm_rom7720_a1/Kconfig"
>> diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig
>> new file mode 100644
>> index 0000000000..b6806b8859
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/Kconfig
>> @@ -0,0 +1,21 @@
>> +if TARGET_IMX8QXP_AI_ML
>> +
>> +config SYS_BOARD
>> + default "imx8qxp_ai_ml"
>> +
>> +config SYS_VENDOR
>> + default "einfochips"
>> +
>> +config SYS_CONFIG_NAME
>> + default "imx8qxp_ai_ml"
>> +
>> +config SYS_MALLOC_LEN
>> + default 0x2400000
>> +
>> +config ENV_SIZE
>> + default 0x1000
>> +
>> +config ENV_OFFSET
>> + default 0x400000
>> +
>> +endif
>> diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>> new file mode 100644
>> index 0000000000..add0bd9431
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +i.MX8QXP AI_ML BOARD
>> +M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> +S: Maintained
>> +F: board/einfochips/imx8qxp_ai_ml/
>> +F: include/configs/imx8qxp_ai_ml.h
>> +F: configs/imx8qxp_ai_ml_defconfig
>> diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile
>> new file mode 100644
>> index 0000000000..e08774dc6e
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/Makefile
>> @@ -0,0 +1,8 @@
>> +#
>> +# Copyright 2019 Linaro Ltd.
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y += imx8qxp_ai_ml.o
>> +obj-$(CONFIG_SPL_BUILD) += spl.o
>> diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README
>> new file mode 100644
>> index 0000000000..488920580f
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/README
>> @@ -0,0 +1,49 @@
>> +U-Boot for the Einfochips i.MX8QXP AI_ML board
>> +
>> +Quick Start
>> +===========
>> +
>> +- Get and Build the ARM Trusted firmware
>> +- Get scfw_tcm.bin and ahab-container.img
>> +- Build U-Boot
>> +- Flash the binary into the SD card
>> +- Boot
>> +
>> +Get and Build the ARM Trusted firmware
>> +======================================
>> +
>> +$ git clone https://source.codeaurora.org/external/imx/imx-atf
>> +$ cd imx-atf/
>> +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
>> +$ make PLAT=imx8qxp bl31
>> +
>> +Get scfw_tcm.bin and ahab-container.img
>> +=======================================
>> +
>> +$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml-scfw-tcm.bin
>> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin
>> +$ chmod +x firmware-imx-8.1.bin
>> +$ ./firmware-imx-8.1.bin
>> +
>> +Copy the following binaries to U-Boot folder:
>> +
>> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
>> +$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img .
>> +
>> +Build U-Boot
>> +============
>> +
>> +$ make imx8qxp_ai_ml_defconfig
>> +$ make u-boot-dtb.imx
>> +
>> +Flash the binary into the SD card
>> +=================================
>> +
>> +Burn the u-boot-dtb.imx binary to SD card offset 32KB:
>> +
>> +$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
>> +
>> +Boot
>> +====
>> +
>> +Set Boot switch SW2: 1100.
>> diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>> new file mode 100644
>> index 0000000000..7ba014ac07
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>> @@ -0,0 +1,78 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2018 NXP
>> + * Copyright 2019 Linaro Ltd.
>> + */
>> +
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <linux/libfdt.h>
>> +#include <fsl_esdhc.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/sci/sci.h>
>> +#include <asm/arch/imx8-pins.h>
>> +#include <asm/arch/iomux.h>
>> +#include <asm/arch/sys_proto.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_early_init_f(void)
>> +{
>> + sc_pm_clock_rate_t rate = SC_80MHZ;
>> + int ret;
>> +
>> + /* Set UART2 clock root to 80 MHz */
>> + ret = sc_pm_setup_uart(SC_R_UART_2, rate);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +
>> +#if IS_ENABLED(CONFIG_FEC_MXC)
>> +#include <miiphy.h>
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>> +
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>> +
>> + if (phydev->drv->config)
>> + phydev->drv->config(phydev);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +int checkboard(void)
>> +{
>> + puts("Board: iMX8QXP AI_ML\n");
>> +
>> + build_info();
>> + print_bootinfo();
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + return 0;
>> +}
>> +
>> +/* Board specific reset that is system reset */
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> + /* TODO */
>> +}
>> +
>> +#ifdef CONFIG_OF_BOARD_SETUP
>> +int ft_board_setup(void *blob, struct bd_info *bd)
>> +{
>> + return 0;
>> +}
>> +#endif
>> diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
>> new file mode 100644
>> index 0000000000..4fc5ade313
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2018 NXP
>> + *
>> + * Refer doc/README.imx8image for more details about how-to configure
>> + * and create imx8image boot image
>> + */
>> +
>> +#define __ASSEMBLY__
>> +
>> +/* Boot from SD, sector size 0x400 */
>> +BOOT_FROM SD 0x400
>> +/* SoC type IMX8QX */
>> +SOC_TYPE IMX8QX
>> +/* Append seco container image */
>> +APPEND mx8qx-ahab-container.img
>> +/* Create the 2nd container */
>> +CONTAINER
>> +/* Add scfw image with exec attribute */
>> +IMAGE SCU mx8qx-aiml-scfw-tcm.bin
>> +/* Add ATF image with exec attribute */
>> +IMAGE A35 bl31.bin 0x80000000
>> +/* Add U-Boot image with load attribute */
>> +DATA A35 u-boot-dtb.bin 0x80020000
>> diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c
>> new file mode 100644
>> index 0000000000..2e6e0741e5
>> --- /dev/null
>> +++ b/board/einfochips/imx8qxp_ai_ml/spl.c
>> @@ -0,0 +1,39 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2018 NXP
>> + * Copyright 2019 Linaro Ltd.
>> + *
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <spl.h>
>> +#include <dm/uclass.h>
>> +#include <dm/device.h>
>> +#include <dm/uclass-internal.h>
>> +#include <dm/device-internal.h>
>> +#include <dm/lists.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +void spl_board_init(void)
>> +{
>> + arch_cpu_init();
>> +
>> + timer_init();
>> +
>> + preloader_console_init();
>> +
>> + puts("Normal Boot\n");
>> +}
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> + /* Clear global data */
>> + memset((void *)gd, 0, sizeof(gd_t));
>> +
>> + /* Clear the BSS. */
>> + memset(__bss_start, 0, __bss_end - __bss_start);
>> +
>> + board_init_r(NULL, 0);
>> +}
>> diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig
>> new file mode 100644
>> index 0000000000..e20a0c783e
>> --- /dev/null
>> +++ b/configs/imx8qxp_ai_ml_defconfig
>> @@ -0,0 +1,83 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_IMX8=y
>> +CONFIG_SYS_TEXT_BASE=0x80020000
>> +CONFIG_DISTRO_DEFAULTS=y
>> +CONFIG_SPL_GPIO_SUPPORT=y
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_SYS_MALLOC_F_LEN=0x4000
>> +CONFIG_TARGET_IMX8QXP_AI_ML=y
>> +CONFIG_SPL_MMC_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
>> +CONFIG_NR_DRAM_BANKS=4
>> +CONFIG_SPL=y
>> +CONFIG_FIT=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg"
>> +CONFIG_BOOTDELAY=3
>> +CONFIG_LOG=y
>> +CONFIG_SPL_BOARD_INIT=y
>> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>> +CONFIG_SPL_SEPARATE_BSS=y
>> +CONFIG_SPL_POWER_SUPPORT=y
>> +CONFIG_SPL_POWER_DOMAIN=y
>> +CONFIG_SPL_WATCHDOG_SUPPORT=y
>> +CONFIG_HUSH_PARSER=y
>> +CONFIG_CMD_CPU=y
>> +# CONFIG_CMD_IMPORTENV is not set
>> +CONFIG_CMD_CLK=y
>> +CONFIG_CMD_DM=y
>> +CONFIG_CMD_FUSE=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_DHCP=y
>> +CONFIG_CMD_MII=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_CMD_EXT4=y
>> +CONFIG_CMD_EXT4_WRITE=y
>> +CONFIG_CMD_FAT=y
>> +CONFIG_FAT_WRITE=y
>> +CONFIG_CMD_FS_GENERIC=y
>> +CONFIG_SPL_OF_CONTROL=y
>> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml"
>> +CONFIG_ENV_IS_IN_MMC=y
>> +CONFIG_SPL_DM=y
>> +CONFIG_SPL_CLK=y
>> +CONFIG_CLK_IMX8=y
>> +CONFIG_CPU=y
>> +CONFIG_DM_GPIO=y
>> +CONFIG_MXC_GPIO=y
>> +CONFIG_DM_I2C=y
>> +CONFIG_SYS_I2C_IMX_LPI2C=y
>> +CONFIG_MISC=y
>> +CONFIG_DM_MMC=y
>> +CONFIG_FSL_ESDHC=y
>> +CONFIG_PHYLIB=y
>> +CONFIG_PHY_ADDR_ENABLE=y
>> +CONFIG_PHY_ATHEROS=y
>> +CONFIG_DM_ETH=y
>> +CONFIG_NET_RANDOM_ETHADDR=y
>> +CONFIG_PHY_GIGE=y
>> +CONFIG_FEC_MXC_SHARE_MDIO=y
>> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
>> +CONFIG_FEC_MXC=y
>> +CONFIG_MII=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_SPL_PINCTRL=y
>> +CONFIG_PINCTRL_IMX8=y
>> +CONFIG_POWER_DOMAIN=y
>> +CONFIG_IMX8_POWER_DOMAIN=y
>> +CONFIG_DM_REGULATOR=y
>> +CONFIG_SPL_DM_REGULATOR=y
>> +CONFIG_DM_REGULATOR_FIXED=y
>> +CONFIG_DM_REGULATOR_GPIO=y
>> +CONFIG_SPL_DM_REGULATOR_GPIO=y
>> +CONFIG_DM_SERIAL=y
>> +CONFIG_FSL_LPUART=y
>> +CONFIG_SPL_TINY_MEMSET=y
>> +# CONFIG_EFI_LOADER is not set
>> diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h
>> new file mode 100644
>> index 0000000000..bdac710103
>> --- /dev/null
>> +++ b/include/configs/imx8qxp_ai_ml.h
>> @@ -0,0 +1,95 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2018 NXP
>> + * Copyright 2019 Linaro Ltd.
>> + */
>> +
>> +#ifndef __IMX8QXP_AI_ML_H
>> +#define __IMX8QXP_AI_ML_H
>> +
>> +#include <linux/sizes.h>
>> +#include <asm/arch/imx-regs.h>
>> +
>> +#ifdef CONFIG_SPL_BUILD
>> +#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
>> +#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K)
>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
>> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
>> +
>> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
>> +#define CONFIG_SPL_STACK 0x013E000
>> +#define CONFIG_SPL_BSS_START_ADDR 0x00128000
>> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */
>> +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
>> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
>> +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000
>> +#define CONFIG_MALLOC_F_ADDR 0x00120000
>> +
>> +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
>> +
>> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
>> +
>> +#define CONFIG_OF_SEPARATE
>> +#endif
>> +
>> +#define CONFIG_REMAKE_ELF
>> +
>> +/* Flat Device Tree Definitions */
>> +#define CONFIG_OF_BOARD_SETUP
>> +
>> +#define CONFIG_FSL_USDHC
>> +
>> +#define CONFIG_ENV_OVERWRITE
>> +
>> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>> +
>> +#define BOOT_TARGET_DEVICES(func) \
>> + func(MMC, mmc, 1) \
>> + func(DHCP, dhcp, na)
>> +
>> +#include <config_distro_bootcmd.h>
>> +/* Initial environment variables */
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "console=ttyLP2 earlycon\0" \
>> + "fdt_addr_r=0x83000000\0" \
>> + "kernel_addr_r=0x81000000\0" \
>> + "ramdisk_addr_r=0x94400000\0" \
>> + "scriptaddr=0x89000000\0" \
>> + "fdtfile=imx8qxp-ai_ml.dtb\0" \
>> + "fdt_high=0xffffffffffffffff\0" \
>> + "image=Image\0" \
>> + "initrd_addr=0x83800000\0" \
>> + "initrd_high=0xffffffffffffffff\0" \
>> + "netargs=setenv bootargs console=${console},${baudrate} " \
>> + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
>> + "\0" \
>> + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
>> + "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
>> + BOOTENV
>> +
>> +/* Link Definitions */
>> +#define CONFIG_LOADADDR 0x80280000
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
>> +
>> +/* USDHC2 is the SD card interface */
>> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>> +
>> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
>> +#define PHYS_SDRAM_1 0x80000000
>> +#define PHYS_SDRAM_2 0x880000000
>> +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
>> +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
>> +
>> +/* Generic Timer Definitions */
>> +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
>> +
>> +/* Networking */
>> +#define CONFIG_FEC_XCV_TYPE RGMII
>> +#define FEC_QUIRK_ENET_MAC
>> +
>> +#endif /* __IMX8QXP_AI_ML_H */
>>
>
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] board: Add support for iMX8QXP AI_ML board
2020-08-03 15:05 ` Stefano Babic
@ 2020-08-03 15:10 ` Stefano Babic
0 siblings, 0 replies; 4+ messages in thread
From: Stefano Babic @ 2020-08-03 15:10 UTC (permalink / raw)
To: u-boot
On 03.08.20 17:05, Stefano Babic wrote:
> On 03.08.20 17:03, Stefano Babic wrote:
>> Hi Mani,
>>
>> On 29.07.20 07:05, Manivannan Sadhasivam wrote:
>>> This commit adds initial board support for iMX8QXP AI_ML board from
>>> Einfochips. This board is one of the 96Boards Consumer Edition and AI
>>> boards of the 96Boards family based on i.MX8QXP SoC from NXP/Freescale.
>>>
>>> This initial supports contains following peripherals which are tested and
>>> known to work:
>>>
>>> 1. Debug serial via UART2
>>> 2. SD card
>>> 3. Ethernet
>>>
>>> More information about this board can be found in arrow website:
>>> https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools
>>>
>>> Reviewed-by: Peng Fan <peng.fan@nxp.com>
>>> Reviewed-by: Fabio Estevam <festevam@gmail.com>
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> ---
>>>
>>
>> I see several errors when building this board
>> https://travis-ci.org/github/sbabic/u-boot-imx/jobs/714193236
>>
>> Anyway, where is the DTS for this board ?
>>
>
> It seems I picked up the wrong version, I check it again..
Ok, now clear - so I archive all versions up to 4, and I am waiting for
V5 with the small changes asked by Lukasz.
Best regards,
Stefano Babic
>
>>
>>> Changes in v2:
>>>
>>> * Rebased onto u-boot/master and fixed one build issue
>>> * Added review from Fabio
>>>
>>> arch/arm/mach-imx/imx8/Kconfig | 6 ++
>>> board/einfochips/imx8qxp_ai_ml/Kconfig | 21 ++++
>>> board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 ++
>>> board/einfochips/imx8qxp_ai_ml/Makefile | 8 ++
>>> board/einfochips/imx8qxp_ai_ml/README | 49 ++++++++++
>>> .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 78 +++++++++++++++
>>> board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++++
>>> board/einfochips/imx8qxp_ai_ml/spl.c | 39 ++++++++
>>> configs/imx8qxp_ai_ml_defconfig | 83 ++++++++++++++++
>>> include/configs/imx8qxp_ai_ml.h | 95 +++++++++++++++++++
>>> 10 files changed, 409 insertions(+)
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/README
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg
>>> create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c
>>> create mode 100644 configs/imx8qxp_ai_ml_defconfig
>>> create mode 100644 include/configs/imx8qxp_ai_ml.h
>>>
>>> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
>>> index 9d1f73dfc7..308122d62a 100644
>>> --- a/arch/arm/mach-imx/imx8/Kconfig
>>> +++ b/arch/arm/mach-imx/imx8/Kconfig
>>> @@ -75,6 +75,11 @@ config TARGET_GIEDI
>>> select BOARD_LATE_INIT
>>> select IMX8QXP
>>>
>>> +config TARGET_IMX8QXP_AI_ML
>>> + bool "Support i.MX8QXP AI_ML board"
>>> + select BOARD_EARLY_INIT_F
>>> + select IMX8QXP
>>> +
>>> config TARGET_IMX8QM_MEK
>>> bool "Support i.MX8QM MEK board"
>>> select BOARD_LATE_INIT
>>> @@ -93,6 +98,7 @@ config TARGET_IMX8QXP_MEK
>>>
>>> endchoice
>>>
>>> +source "board/einfochips/imx8qxp_ai_ml/Kconfig"
>>> source "board/freescale/imx8qm_mek/Kconfig"
>>> source "board/freescale/imx8qxp_mek/Kconfig"
>>> source "board/advantech/imx8qm_rom7720_a1/Kconfig"
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/Kconfig b/board/einfochips/imx8qxp_ai_ml/Kconfig
>>> new file mode 100644
>>> index 0000000000..b6806b8859
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/Kconfig
>>> @@ -0,0 +1,21 @@
>>> +if TARGET_IMX8QXP_AI_ML
>>> +
>>> +config SYS_BOARD
>>> + default "imx8qxp_ai_ml"
>>> +
>>> +config SYS_VENDOR
>>> + default "einfochips"
>>> +
>>> +config SYS_CONFIG_NAME
>>> + default "imx8qxp_ai_ml"
>>> +
>>> +config SYS_MALLOC_LEN
>>> + default 0x2400000
>>> +
>>> +config ENV_SIZE
>>> + default 0x1000
>>> +
>>> +config ENV_OFFSET
>>> + default 0x400000
>>> +
>>> +endif
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/MAINTAINERS b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>>> new file mode 100644
>>> index 0000000000..add0bd9431
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/MAINTAINERS
>>> @@ -0,0 +1,6 @@
>>> +i.MX8QXP AI_ML BOARD
>>> +M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> +S: Maintained
>>> +F: board/einfochips/imx8qxp_ai_ml/
>>> +F: include/configs/imx8qxp_ai_ml.h
>>> +F: configs/imx8qxp_ai_ml_defconfig
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/Makefile b/board/einfochips/imx8qxp_ai_ml/Makefile
>>> new file mode 100644
>>> index 0000000000..e08774dc6e
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/Makefile
>>> @@ -0,0 +1,8 @@
>>> +#
>>> +# Copyright 2019 Linaro Ltd.
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-y += imx8qxp_ai_ml.o
>>> +obj-$(CONFIG_SPL_BUILD) += spl.o
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/README b/board/einfochips/imx8qxp_ai_ml/README
>>> new file mode 100644
>>> index 0000000000..488920580f
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/README
>>> @@ -0,0 +1,49 @@
>>> +U-Boot for the Einfochips i.MX8QXP AI_ML board
>>> +
>>> +Quick Start
>>> +===========
>>> +
>>> +- Get and Build the ARM Trusted firmware
>>> +- Get scfw_tcm.bin and ahab-container.img
>>> +- Build U-Boot
>>> +- Flash the binary into the SD card
>>> +- Boot
>>> +
>>> +Get and Build the ARM Trusted firmware
>>> +======================================
>>> +
>>> +$ git clone https://source.codeaurora.org/external/imx/imx-atf
>>> +$ cd imx-atf/
>>> +$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
>>> +$ make PLAT=imx8qxp bl31
>>> +
>>> +Get scfw_tcm.bin and ahab-container.img
>>> +=======================================
>>> +
>>> +$ wget https://raw.githubusercontent.com/96boards-ai-ml/binaries/master/mx8qx-aiml-scfw-tcm.bin
>>> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.1.bin
>>> +$ chmod +x firmware-imx-8.1.bin
>>> +$ ./firmware-imx-8.1.bin
>>> +
>>> +Copy the following binaries to U-Boot folder:
>>> +
>>> +$ cp imx-atf/build/imx8qxp/release/bl31.bin .
>>> +$ cp firmware-imx-8.1/firmware/seco/mx8qx-ahab-container.img .
>>> +
>>> +Build U-Boot
>>> +============
>>> +
>>> +$ make imx8qxp_ai_ml_defconfig
>>> +$ make u-boot-dtb.imx
>>> +
>>> +Flash the binary into the SD card
>>> +=================================
>>> +
>>> +Burn the u-boot-dtb.imx binary to SD card offset 32KB:
>>> +
>>> +$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
>>> +
>>> +Boot
>>> +====
>>> +
>>> +Set Boot switch SW2: 1100.
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>>> new file mode 100644
>>> index 0000000000..7ba014ac07
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c
>>> @@ -0,0 +1,78 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2018 NXP
>>> + * Copyright 2019 Linaro Ltd.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <errno.h>
>>> +#include <linux/libfdt.h>
>>> +#include <fsl_esdhc.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/sci/sci.h>
>>> +#include <asm/arch/imx8-pins.h>
>>> +#include <asm/arch/iomux.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +int board_early_init_f(void)
>>> +{
>>> + sc_pm_clock_rate_t rate = SC_80MHZ;
>>> + int ret;
>>> +
>>> + /* Set UART2 clock root to 80 MHz */
>>> + ret = sc_pm_setup_uart(SC_R_UART_2, rate);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +#if IS_ENABLED(CONFIG_FEC_MXC)
>>> +#include <miiphy.h>
>>> +
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
>>> +
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
>>> +
>>> + if (phydev->drv->config)
>>> + phydev->drv->config(phydev);
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +int checkboard(void)
>>> +{
>>> + puts("Board: iMX8QXP AI_ML\n");
>>> +
>>> + build_info();
>>> + print_bootinfo();
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int board_init(void)
>>> +{
>>> + return 0;
>>> +}
>>> +
>>> +/* Board specific reset that is system reset */
>>> +
>>> +void reset_cpu(ulong addr)
>>> +{
>>> + /* TODO */
>>> +}
>>> +
>>> +#ifdef CONFIG_OF_BOARD_SETUP
>>> +int ft_board_setup(void *blob, struct bd_info *bd)
>>> +{
>>> + return 0;
>>> +}
>>> +#endif
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/imximage.cfg b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
>>> new file mode 100644
>>> index 0000000000..4fc5ade313
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/imximage.cfg
>>> @@ -0,0 +1,24 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright 2018 NXP
>>> + *
>>> + * Refer doc/README.imx8image for more details about how-to configure
>>> + * and create imx8image boot image
>>> + */
>>> +
>>> +#define __ASSEMBLY__
>>> +
>>> +/* Boot from SD, sector size 0x400 */
>>> +BOOT_FROM SD 0x400
>>> +/* SoC type IMX8QX */
>>> +SOC_TYPE IMX8QX
>>> +/* Append seco container image */
>>> +APPEND mx8qx-ahab-container.img
>>> +/* Create the 2nd container */
>>> +CONTAINER
>>> +/* Add scfw image with exec attribute */
>>> +IMAGE SCU mx8qx-aiml-scfw-tcm.bin
>>> +/* Add ATF image with exec attribute */
>>> +IMAGE A35 bl31.bin 0x80000000
>>> +/* Add U-Boot image with load attribute */
>>> +DATA A35 u-boot-dtb.bin 0x80020000
>>> diff --git a/board/einfochips/imx8qxp_ai_ml/spl.c b/board/einfochips/imx8qxp_ai_ml/spl.c
>>> new file mode 100644
>>> index 0000000000..2e6e0741e5
>>> --- /dev/null
>>> +++ b/board/einfochips/imx8qxp_ai_ml/spl.c
>>> @@ -0,0 +1,39 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright 2018 NXP
>>> + * Copyright 2019 Linaro Ltd.
>>> + *
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <spl.h>
>>> +#include <dm/uclass.h>
>>> +#include <dm/device.h>
>>> +#include <dm/uclass-internal.h>
>>> +#include <dm/device-internal.h>
>>> +#include <dm/lists.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +void spl_board_init(void)
>>> +{
>>> + arch_cpu_init();
>>> +
>>> + timer_init();
>>> +
>>> + preloader_console_init();
>>> +
>>> + puts("Normal Boot\n");
>>> +}
>>> +
>>> +void board_init_f(ulong dummy)
>>> +{
>>> + /* Clear global data */
>>> + memset((void *)gd, 0, sizeof(gd_t));
>>> +
>>> + /* Clear the BSS. */
>>> + memset(__bss_start, 0, __bss_end - __bss_start);
>>> +
>>> + board_init_r(NULL, 0);
>>> +}
>>> diff --git a/configs/imx8qxp_ai_ml_defconfig b/configs/imx8qxp_ai_ml_defconfig
>>> new file mode 100644
>>> index 0000000000..e20a0c783e
>>> --- /dev/null
>>> +++ b/configs/imx8qxp_ai_ml_defconfig
>>> @@ -0,0 +1,83 @@
>>> +CONFIG_ARM=y
>>> +CONFIG_ARCH_IMX8=y
>>> +CONFIG_SYS_TEXT_BASE=0x80020000
>>> +CONFIG_DISTRO_DEFAULTS=y
>>> +CONFIG_SPL_GPIO_SUPPORT=y
>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>> +CONFIG_SYS_MALLOC_F_LEN=0x4000
>>> +CONFIG_TARGET_IMX8QXP_AI_ML=y
>>> +CONFIG_SPL_MMC_SUPPORT=y
>>> +CONFIG_SPL_SERIAL_SUPPORT=y
>>> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
>>> +CONFIG_NR_DRAM_BANKS=4
>>> +CONFIG_SPL=y
>>> +CONFIG_FIT=y
>>> +CONFIG_SPL_LOAD_FIT=y
>>> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
>>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/einfochips/imx8qxp_ai_ml/imximage.cfg"
>>> +CONFIG_BOOTDELAY=3
>>> +CONFIG_LOG=y
>>> +CONFIG_SPL_BOARD_INIT=y
>>> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
>>> +CONFIG_SPL_SEPARATE_BSS=y
>>> +CONFIG_SPL_POWER_SUPPORT=y
>>> +CONFIG_SPL_POWER_DOMAIN=y
>>> +CONFIG_SPL_WATCHDOG_SUPPORT=y
>>> +CONFIG_HUSH_PARSER=y
>>> +CONFIG_CMD_CPU=y
>>> +# CONFIG_CMD_IMPORTENV is not set
>>> +CONFIG_CMD_CLK=y
>>> +CONFIG_CMD_DM=y
>>> +CONFIG_CMD_FUSE=y
>>> +CONFIG_CMD_GPIO=y
>>> +CONFIG_CMD_GPT=y
>>> +CONFIG_CMD_I2C=y
>>> +CONFIG_CMD_MMC=y
>>> +CONFIG_CMD_DHCP=y
>>> +CONFIG_CMD_MII=y
>>> +CONFIG_CMD_PING=y
>>> +CONFIG_CMD_CACHE=y
>>> +CONFIG_CMD_EXT4=y
>>> +CONFIG_CMD_EXT4_WRITE=y
>>> +CONFIG_CMD_FAT=y
>>> +CONFIG_FAT_WRITE=y
>>> +CONFIG_CMD_FS_GENERIC=y
>>> +CONFIG_SPL_OF_CONTROL=y
>>> +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-ai_ml"
>>> +CONFIG_ENV_IS_IN_MMC=y
>>> +CONFIG_SPL_DM=y
>>> +CONFIG_SPL_CLK=y
>>> +CONFIG_CLK_IMX8=y
>>> +CONFIG_CPU=y
>>> +CONFIG_DM_GPIO=y
>>> +CONFIG_MXC_GPIO=y
>>> +CONFIG_DM_I2C=y
>>> +CONFIG_SYS_I2C_IMX_LPI2C=y
>>> +CONFIG_MISC=y
>>> +CONFIG_DM_MMC=y
>>> +CONFIG_FSL_ESDHC=y
>>> +CONFIG_PHYLIB=y
>>> +CONFIG_PHY_ADDR_ENABLE=y
>>> +CONFIG_PHY_ATHEROS=y
>>> +CONFIG_DM_ETH=y
>>> +CONFIG_NET_RANDOM_ETHADDR=y
>>> +CONFIG_PHY_GIGE=y
>>> +CONFIG_FEC_MXC_SHARE_MDIO=y
>>> +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
>>> +CONFIG_FEC_MXC=y
>>> +CONFIG_MII=y
>>> +CONFIG_PINCTRL=y
>>> +CONFIG_SPL_PINCTRL=y
>>> +CONFIG_PINCTRL_IMX8=y
>>> +CONFIG_POWER_DOMAIN=y
>>> +CONFIG_IMX8_POWER_DOMAIN=y
>>> +CONFIG_DM_REGULATOR=y
>>> +CONFIG_SPL_DM_REGULATOR=y
>>> +CONFIG_DM_REGULATOR_FIXED=y
>>> +CONFIG_DM_REGULATOR_GPIO=y
>>> +CONFIG_SPL_DM_REGULATOR_GPIO=y
>>> +CONFIG_DM_SERIAL=y
>>> +CONFIG_FSL_LPUART=y
>>> +CONFIG_SPL_TINY_MEMSET=y
>>> +# CONFIG_EFI_LOADER is not set
>>> diff --git a/include/configs/imx8qxp_ai_ml.h b/include/configs/imx8qxp_ai_ml.h
>>> new file mode 100644
>>> index 0000000000..bdac710103
>>> --- /dev/null
>>> +++ b/include/configs/imx8qxp_ai_ml.h
>>> @@ -0,0 +1,95 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright 2018 NXP
>>> + * Copyright 2019 Linaro Ltd.
>>> + */
>>> +
>>> +#ifndef __IMX8QXP_AI_ML_H
>>> +#define __IMX8QXP_AI_ML_H
>>> +
>>> +#include <linux/sizes.h>
>>> +#include <asm/arch/imx-regs.h>
>>> +
>>> +#ifdef CONFIG_SPL_BUILD
>>> +#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
>>> +#define CONFIG_SYS_MONITOR_LEN (SZ_1K * SZ_1K)
>>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
>>> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
>>> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
>>> +
>>> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
>>> +#define CONFIG_SPL_STACK 0x013E000
>>> +#define CONFIG_SPL_BSS_START_ADDR 0x00128000
>>> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */
>>> +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
>>> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
>>> +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000
>>> +#define CONFIG_MALLOC_F_ADDR 0x00120000
>>> +
>>> +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
>>> +
>>> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
>>> +
>>> +#define CONFIG_OF_SEPARATE
>>> +#endif
>>> +
>>> +#define CONFIG_REMAKE_ELF
>>> +
>>> +/* Flat Device Tree Definitions */
>>> +#define CONFIG_OF_BOARD_SETUP
>>> +
>>> +#define CONFIG_FSL_USDHC
>>> +
>>> +#define CONFIG_ENV_OVERWRITE
>>> +
>>> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> +
>>> +#define BOOT_TARGET_DEVICES(func) \
>>> + func(MMC, mmc, 1) \
>>> + func(DHCP, dhcp, na)
>>> +
>>> +#include <config_distro_bootcmd.h>
>>> +/* Initial environment variables */
>>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>>> + "console=ttyLP2 earlycon\0" \
>>> + "fdt_addr_r=0x83000000\0" \
>>> + "kernel_addr_r=0x81000000\0" \
>>> + "ramdisk_addr_r=0x94400000\0" \
>>> + "scriptaddr=0x89000000\0" \
>>> + "fdtfile=imx8qxp-ai_ml.dtb\0" \
>>> + "fdt_high=0xffffffffffffffff\0" \
>>> + "image=Image\0" \
>>> + "initrd_addr=0x83800000\0" \
>>> + "initrd_high=0xffffffffffffffff\0" \
>>> + "netargs=setenv bootargs console=${console},${baudrate} " \
>>> + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
>>> + "\0" \
>>> + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
>>> + "imx8qxp-ai_ml/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
>>> + BOOTENV
>>> +
>>> +/* Link Definitions */
>>> +#define CONFIG_LOADADDR 0x80280000
>>> +
>>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>>> +
>>> +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
>>> +
>>> +/* USDHC2 is the SD card interface */
>>> +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
>>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>>> +
>>> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
>>> +#define PHYS_SDRAM_1 0x80000000
>>> +#define PHYS_SDRAM_2 0x880000000
>>> +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
>>> +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
>>> +
>>> +/* Generic Timer Definitions */
>>> +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
>>> +
>>> +/* Networking */
>>> +#define CONFIG_FEC_XCV_TYPE RGMII
>>> +#define FEC_QUIRK_ENET_MAC
>>> +
>>> +#endif /* __IMX8QXP_AI_ML_H */
>>>
>>
>>
>
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
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2020-07-29 5:05 [PATCH v2] board: Add support for iMX8QXP AI_ML board Manivannan Sadhasivam
2020-08-03 15:03 ` Stefano Babic
2020-08-03 15:05 ` Stefano Babic
2020-08-03 15:10 ` Stefano Babic
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