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([2602:47:d48c:8101:c606:9489:98df:6a3b]) by smtp.gmail.com with ESMTPSA id b1-20020a170903228100b001867fdec154sm2181773plh.224.2022.12.16.16.13.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Dec 2022 16:13:46 -0800 (PST) Message-ID: <7f555a78-1533-7be6-f627-6e594a19c04d@linaro.org> Date: Fri, 16 Dec 2022 16:13:45 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 3/5] target/arm: wrap semihosting and psci calls with tcg_enabled Content-Language: en-US To: Fabiano Rosas , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost References: <20221216212944.28229-1-farosas@suse.de> <20221216212944.28229-4-farosas@suse.de> From: Richard Henderson In-Reply-To: <20221216212944.28229-4-farosas@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/16/22 13:29, Fabiano Rosas wrote: > - if (arm_is_psci_call(cpu, cs->exception_index)) { > - arm_handle_psci_call(cpu); > - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); > - return; > - } > + if (tcg_enabled()) { > + if (arm_is_psci_call(cpu, cs->exception_index)) { This could be if (tcg_enabled() && arm_is_psci_call(...)) because... > - /* > - * Semihosting semantics depend on the register width of the code > - * that caused the exception, not the target exception level, so > - * must be handled here. > - */ > + /* > + * Semihosting semantics depend on the register width of the code > + * that caused the exception, not the target exception level, so > + * must be handled here. > + */ > #ifdef CONFIG_TCG > - if (cs->exception_index == EXCP_SEMIHOST) { > - tcg_handle_semihosting(cs); > - return; > - } > + if (cs->exception_index == EXCP_SEMIHOST) { If you were able to replace the ifdef, that would be one thing, but since you aren't I don't think this requires a separate check. There is no way to generate EXCP_SEMIHOST except via TCG. I guess I don't insist, since you're working toward Claudio's much larger patch set, so Reviewed-by: Richard Henderson r~