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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id e5sm11235978wrd.1.2021.09.25.07.20.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Sep 2021 07:20:58 -0700 (PDT) Message-ID: <7fd67b93-3fe6-ceb6-52d0-d5ddaf2d158c@amsat.org> Date: Sat, 25 Sep 2021 16:20:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH v6 00/40] accel: Move has_work() from CPUClass to AccelOpsClass Content-Language: en-US To: qemu-devel@nongnu.org References: <20210924093847.1014331-1-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20210924093847.1014331-1-f4bug@amsat.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/24/21 11:38, Philippe Mathieu-Daudé wrote: > CPU has_work() is a per-accelerator handler. This series is organized > in 2 parts: > - Patches 1-15: Move has_work() from CPUClass to AccelOpsClass > - Patches 16-40: Move remainging has_work() to TCGCPUOps > target/arm: Explicit v7M cores use arm_cpu_has_work as > CPUClass:has_work > target/arm: Restrict has_work() handler to sysemu and TCG Apparently while reworking the target/arm patch I dropped the target/alpha one, so I have to respin this properly. (Note however I noticed that locally rebasing my branch on the recent tcg-next merged tag, and this series did pass the CI, so I wonder if qemu-alpha is built / tested in CI... I'll look at it later). > target/avr: Restrict has_work() handler to sysemu > target/cris: Restrict has_work() handler to sysemu > target/hexagon: Remove unused has_work() handler > target/hppa: Restrict has_work() handler to sysemu > target/i386: Restrict has_work() handler to sysemu and TCG > target/m68k: Restrict has_work() handler to sysemu > target/microblaze: Restrict has_work() handler to sysemu > target/mips: Restrict has_work() handler to sysemu and TCG > target/nios2: Restrict has_work() handler to sysemu > target/openrisc: Restrict has_work() handler to sysemu > target/ppc: Introduce PowerPCCPUClass::has_work() > target/ppc: Restrict has_work() handlers to sysemu and TCG > target/riscv: Restrict has_work() handler to sysemu and TCG > target/rx: Restrict has_work() handler to sysemu > target/s390x: Restrict has_work() handler to sysemu and TCG > target/sh4: Restrict has_work() handler to sysemu > target/sparc: Remove pointless use of CONFIG_TCG definition > target/sparc: Restrict has_work() handler to sysemu > target/tricore: Restrict has_work() handler to sysemu > target/xtensa: Restrict has_work() handler to sysemu > accel/tcg: Remove CPUClass::has_work() > accel/tcg: Simplify tcg_cpu_has_work()