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From: Russ Weight <russell.h.weight@intel.com>
To: Xu Yilun <yilun.xu@intel.com>
Cc: mdf@kernel.org, linux-fpga@vger.kernel.org, trix@redhat.com,
	lgoncalv@redhat.com, hao.wu@intel.com, matthew.gerlach@intel.com,
	richard.gong@intel.com
Subject: Re: [PATCH v6 2/3] fpga: bridge: Use standard dev_release for class driver
Date: Tue, 22 Jun 2021 16:05:39 -0700	[thread overview]
Message-ID: <7fdea841-dad0-8b73-0313-3a1c3dfaa17f@intel.com> (raw)
In-Reply-To: <20210622082301.GA29169@yilunxu-OptiPlex-7050>



On 6/22/21 1:23 AM, Xu Yilun wrote:
> 2 more comments.
>
> On Mon, Jun 21, 2021 at 03:22:48PM -0700, Russ Weight wrote:
>> The FPGA bridge class driver data structure is being treated as a
>> managed resource instead of using standard dev_release call-back
>> to release the class data structure. This change removes the
>> managed resource code and combines the create() and register()
>> functions into a single register() function.
>>
>> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
>> ---
>> v6:
>>   - Changed fpga_bridge_register() parameters to accept an info data
>>     structure to provide flexibility in passing optional parameters.
>>   - Added fpga_bridge_register_simple() function to support current
>>     parameters for users that don't require the use of optional
>>     parameters.
> Add the _simple() description in commit message if needed.
>
>> +struct fpga_bridge *
>> +fpga_bridge_register_simple(struct device *dev, const char *name,
> 			       struct device *parent,

Yes - I'll make these changes.

Thanks,
- Russ
>
>> +			    const struct fpga_bridge_ops *br_ops,
>> +			    void *priv);
>> +void fpga_bridge_unregister(struct fpga_bridge *br);
>>  
>>  #endif /* _LINUX_FPGA_BRIDGE_H */
>> -- 
>> 2.25.1


  reply	other threads:[~2021-06-22 23:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-21 22:22 [PATCH v6 0/3] fpga: Use standard class dev_release function Russ Weight
2021-06-21 22:22 ` [PATCH v6 1/3] fpga: mgr: Use standard dev_release for class driver Russ Weight
2021-06-22  7:32   ` Xu Yilun
2021-06-22 22:32     ` Russ Weight
2021-06-22  8:45   ` Xu Yilun
2021-06-22 22:41     ` Russ Weight
2021-06-21 22:22 ` [PATCH v6 2/3] fpga: bridge: " Russ Weight
2021-06-22  8:02   ` Xu Yilun
2021-06-22 23:04     ` Russ Weight
2021-06-22  8:23   ` Xu Yilun
2021-06-22 23:05     ` Russ Weight [this message]
2021-06-21 22:22 ` [PATCH v6 3/3] fpga: region: " Russ Weight
2021-06-22  8:19   ` Xu Yilun
2021-06-22 23:08     ` Russ Weight

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