From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750892AbbDAEDj (ORCPT ); Wed, 1 Apr 2015 00:03:39 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:35077 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750739AbbDAEDe (ORCPT ); Wed, 1 Apr 2015 00:03:34 -0400 From: Kevin Hilman To: Abhilash Kesavan Cc: Javier Martinez Canillas , Tomasz Figa , Stephen Boyd , Mike Turquette , Sylwester Nawrocki , Kukjin Kim , Olof Johansson , Doug Anderson , Krzysztof Kozlowski , Tyler Baker , Chanwoo Choi , linux-arm-kernel , "linux-samsung-soc\@vger.kernel.org" , linux-kernel Subject: Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend References: <1427730803-28635-1-git-send-email-javier.martinez@collabora.co.uk> <1427730803-28635-3-git-send-email-javier.martinez@collabora.co.uk> <551976F1.1000605@collabora.co.uk> <7hiodg98z7.fsf@deeprootsystems.com> Date: Tue, 31 Mar 2015 21:03:31 -0700 In-Reply-To: (Abhilash Kesavan's message of "Wed, 1 Apr 2015 08:49:14 +0530") Message-ID: <7h1tk47awc.fsf@deeprootsystems.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Abhilash Kesavan writes: > On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote: >> Javier Martinez Canillas writes: >> >> [...] >> >>> Unfortunately I don't fully understand why this clock needs to be >>> enabled. It would be good if someone at Samsung can explain in more >>> detail what the real problem really is. >> >> +1 >> >> Maybe Abhilash can shed some light here? >> >> We really should know *why* this is needed because having the fix in the >> clock driver just doesn't seem right. It seems like the DMA driver >> should be managing this clock. > > I think my last mail might not have reached you (was accidentally sent > as html). Yeah, I saw it a bit later in Javier's reply. Thanks for doing the research and reporting back. > We are gating the aclk266_g2d clock without checking the > CG_STATUS0 register bits as specified in the UM. It looks like we need > to keep several clocks alive or gate them only after checking the > CG_STATUSx register bits. I dont' know much about this clock hardware, but to me it sounds like a clock driver bug. The suspend fix Javier is proposing would fix it, but to me it sounds like the clock driver needs to actually start checking these CG_STATUSx bits before gating clocks. Otherwise, we might fix this current bug but a similar one will come and bite us another day. Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend Date: Tue, 31 Mar 2015 21:03:31 -0700 Message-ID: <7h1tk47awc.fsf@deeprootsystems.com> References: <1427730803-28635-1-git-send-email-javier.martinez@collabora.co.uk> <1427730803-28635-3-git-send-email-javier.martinez@collabora.co.uk> <551976F1.1000605@collabora.co.uk> <7hiodg98z7.fsf@deeprootsystems.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Received: from mail-pa0-f45.google.com ([209.85.220.45]:34619 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750726AbbDAEDe (ORCPT ); Wed, 1 Apr 2015 00:03:34 -0400 Received: by pactp5 with SMTP id tp5so39631535pac.1 for ; Tue, 31 Mar 2015 21:03:34 -0700 (PDT) In-Reply-To: (Abhilash Kesavan's message of "Wed, 1 Apr 2015 08:49:14 +0530") Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Abhilash Kesavan Cc: Javier Martinez Canillas , Tomasz Figa , Stephen Boyd , Mike Turquette , Sylwester Nawrocki , Kukjin Kim , Olof Johansson , Doug Anderson , Krzysztof Kozlowski , Tyler Baker , Chanwoo Choi , linux-arm-kernel , "linux-samsung-soc@vger.kernel.org" , linux-kernel Abhilash Kesavan writes: > On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote: >> Javier Martinez Canillas writes: >> >> [...] >> >>> Unfortunately I don't fully understand why this clock needs to be >>> enabled. It would be good if someone at Samsung can explain in more >>> detail what the real problem really is. >> >> +1 >> >> Maybe Abhilash can shed some light here? >> >> We really should know *why* this is needed because having the fix in the >> clock driver just doesn't seem right. It seems like the DMA driver >> should be managing this clock. > > I think my last mail might not have reached you (was accidentally sent > as html). Yeah, I saw it a bit later in Javier's reply. Thanks for doing the research and reporting back. > We are gating the aclk266_g2d clock without checking the > CG_STATUS0 register bits as specified in the UM. It looks like we need > to keep several clocks alive or gate them only after checking the > CG_STATUSx register bits. I dont' know much about this clock hardware, but to me it sounds like a clock driver bug. The suspend fix Javier is proposing would fix it, but to me it sounds like the clock driver needs to actually start checking these CG_STATUSx bits before gating clocks. Otherwise, we might fix this current bug but a similar one will come and bite us another day. Kevin From mboxrd@z Thu Jan 1 00:00:00 1970 From: khilman@kernel.org (Kevin Hilman) Date: Tue, 31 Mar 2015 21:03:31 -0700 Subject: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend In-Reply-To: (Abhilash Kesavan's message of "Wed, 1 Apr 2015 08:49:14 +0530") References: <1427730803-28635-1-git-send-email-javier.martinez@collabora.co.uk> <1427730803-28635-3-git-send-email-javier.martinez@collabora.co.uk> <551976F1.1000605@collabora.co.uk> <7hiodg98z7.fsf@deeprootsystems.com> Message-ID: <7h1tk47awc.fsf@deeprootsystems.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Abhilash Kesavan writes: > On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman wrote: >> Javier Martinez Canillas writes: >> >> [...] >> >>> Unfortunately I don't fully understand why this clock needs to be >>> enabled. It would be good if someone at Samsung can explain in more >>> detail what the real problem really is. >> >> +1 >> >> Maybe Abhilash can shed some light here? >> >> We really should know *why* this is needed because having the fix in the >> clock driver just doesn't seem right. It seems like the DMA driver >> should be managing this clock. > > I think my last mail might not have reached you (was accidentally sent > as html). Yeah, I saw it a bit later in Javier's reply. Thanks for doing the research and reporting back. > We are gating the aclk266_g2d clock without checking the > CG_STATUS0 register bits as specified in the UM. It looks like we need > to keep several clocks alive or gate them only after checking the > CG_STATUSx register bits. I dont' know much about this clock hardware, but to me it sounds like a clock driver bug. The suspend fix Javier is proposing would fix it, but to me it sounds like the clock driver needs to actually start checking these CG_STATUSx bits before gating clocks. Otherwise, we might fix this current bug but a similar one will come and bite us another day. Kevin