Re: [PATCH] x86 hvm: freeze PIT/LAPIC timer emulation while its IRQ is masked

[Kouya Shimura <kouya@jp.fujitsu.com>]

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I remade the patch and measured the performance win. Attached is
a benchmark program which I wrote. It is complied by cygwin's gcc
by -O2 and runs on Windows XP(32bit). And my cpu is 
Intel Core2 Quad Q9450@2.66GHz.

The result is that my patch saves 32 cycles(TSC) per one VM_EXIT(cpuid).
(2696 tsc => 2664 tsc)

The patch is split to two. I'll post them in another mail.

Thanks,
Kouya

Keir Fraser writes:
> On 10/09/2009 10:54, "Kouya Shimura" <kouya@jp.fujitsu.com> wrote:
> 
> >> Not using pt_irq_masked() seems odd. Is it to avoid 859 IRQ mask checks, and
> >> if so why are you doing that? Why do we care that rombios twiddles the 8259
> >> masks a bunch during boot?
> > 
> > I guessed that the cost of freezing/thawing a timer with the 8259 mask
> > is higher than timer emulation.  And the PIT timer is actually active
> > while rombios masks the 8259.
> > 
> > If using pt_irq_masked() is desirable, I'll remake it.
> 
> If your patch works without even any theoretical lost of correctness, then
> that makes it more attractive, obviously.
> 
> Some evidence that the cost saving is at all measurable would also be good.
> Premature optimisation being evil, etc. ;-)
> 
>  -- Keir


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#include <stdio.h>
#include <stdint.h>

#define rdtsc(val) asm volatile("rdtsc" : "=a" (val))

static void cpuid(uint32_t idx)
{
    uint32_t a,b,c,d;
    asm volatile("cpuid": "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(idx) );
}

main()
{
    uint32_t tsc1, tsc2;
    while(1) {
	rdtsc(tsc1);
	cpuid(0x40000000);
	rdtsc(tsc2);
	printf("tsc=%d\n", tsc2 - tsc1);
    }
}

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