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From: "Michel Dänzer" <michel-otUistvHUpPR7s880joybQ@public.gmane.org>
To: christian.koenig-5C7GfCeVMHo@public.gmane.org,
	Andrey Grodzovsky
	<andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
Cc: Alexander.Deucher-5C7GfCeVMHo@public.gmane.org,
	hersenxs.wu-5C7GfCeVMHo@public.gmane.org,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	shirish.s-5C7GfCeVMHo@public.gmane.org
Subject: Re: [PATCH v5 4/4] drm/amd/display: enable S/G for RAVEN chip
Date: Fri, 26 Jul 2019 11:03:20 +0200	[thread overview]
Message-ID: <8046a45b-bf49-ad47-8902-ad928dcc97b4@daenzer.net> (raw)
In-Reply-To: <a1e2755c-142c-ceaf-9be4-1ffff4d25cea-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On 2019-07-26 9:14 a.m., Christian König wrote:
> Am 25.07.19 um 16:24 schrieb Andrey Grodzovsky:
>> From: Shirish S <shirish.s@amd.com>
>>
>> enables gpu_vm_support in dm and adds
>> AMDGPU_GEM_DOMAIN_GTT as supported domain
>>
>> v2:
>> Move BO placement logic into amdgpu_display_supported_domains
>>
>> v3:
>> Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
>>
>> v4:
>> amdgpu_bo_validate_uswc moved to sepperate patch.
>>
>> Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
>> Signed-off-by: Shirish S <shirish.s@amd.com>
>> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 2 +-
>>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>>   2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index cac9975..73045a3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -505,7 +505,7 @@ uint32_t amdgpu_display_supported_domains(struct
>> amdgpu_device *adev)
>>        * APUs. So force the BO placement to VRAM in case this
>> architecture
>>        * will not allow USWC mappings.
>>        */
>> -    if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
>> CHIP_RAVEN &&
>> +    if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <=
>> CHIP_RAVEN &&
> 
> This whole approach is incorrect since we don't check the flags of the
> actually BO used for scanout any more.
> 
> As I wrote before it is still perfectly possible and valid that
> userspace never sets this flag.

Oh right, now I get what you meant before!

I guess amdgpu_display_supported_domains needs to take the BO flags as a
parameter, and also check that AMDGPU_GEM_CREATE_CPU_GTT_USWC is
actually set.


-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2019-07-26  9:03 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-25 14:24 [PATCH v5 0/4] Enable S/G for Picasso Andrey Grodzovsky
     [not found] ` <1564064683-31796-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-07-25 14:24   ` [PATCH v5 1/4] drm/amdgpu: Fix hard hang for S/G display BOs Andrey Grodzovsky
2019-07-25 14:24   ` [PATCH v5 2/4] drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC Andrey Grodzovsky
     [not found]     ` <1564064683-31796-3-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-07-26  7:11       ` Christian König
     [not found]         ` <1723b531-097f-2687-6dc9-9de6e3e378a1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-07-26  8:54           ` Michel Dänzer
     [not found]             ` <fdf2600a-b0ef-bdca-f22b-51427bef9531-otUistvHUpPR7s880joybQ@public.gmane.org>
2019-07-26 11:55               ` Christian König
     [not found]                 ` <881edbab-df57-a1d7-bcf3-987fdbb384db-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-07-26 14:53                   ` Michel Dänzer
     [not found]                     ` <7c62edf1-0e3b-d57e-fd33-f98198b6c23a-otUistvHUpPR7s880joybQ@public.gmane.org>
2019-07-26 16:02                       ` Christian König
     [not found]                         ` <973beeaf-735c-777d-c493-cdfdde2dd2f1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-07-26 16:09                           ` Michel Dänzer
2019-07-25 14:24   ` [PATCH v5 3/4] drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domains Andrey Grodzovsky
2019-07-25 14:24   ` [PATCH v5 4/4] drm/amd/display: enable S/G for RAVEN chip Andrey Grodzovsky
     [not found]     ` <1564064683-31796-5-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-07-25 14:33       ` Kazlauskas, Nicholas
2019-07-26  7:14       ` Christian König
     [not found]         ` <a1e2755c-142c-ceaf-9be4-1ffff4d25cea-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-07-26  9:03           ` Michel Dänzer [this message]
     [not found]             ` <8046a45b-bf49-ad47-8902-ad928dcc97b4-otUistvHUpPR7s880joybQ@public.gmane.org>
2019-07-26 12:47               ` Grodzovsky, Andrey
2019-07-25 14:39   ` [PATCH v5 0/4] Enable S/G for Picasso Michel Dänzer

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