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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Mars Cheng <mars.cheng@mediatek.com>, Rob Herring <robh+dt@kernel.org>
Cc: CC Hwang <cc.hwang@mediatek.com>,
	Loda Chou <loda.chou@mediatek.com>,
	Miles Chen <miles.chen@mediatek.com>,
	Jades Shih <jades.shih@mediatek.com>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	My Chuang <my.chuang@mediatek.com>,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	devicetree@vger.kernel.org, wsd_upstream@mediatek.com
Subject: Re: [PATCH 2/2] arm64: dts: mediatek: add mt6765 support
Date: Fri, 15 Jun 2018 10:54:18 +0200	[thread overview]
Message-ID: <80bca2ae-eb08-3d6c-a863-140107286b2d@gmail.com> (raw)
In-Reply-To: <1528843243-29782-3-git-send-email-mars.cheng@mediatek.com>



On 13/06/18 00:40, Mars Cheng wrote:
> +
> +	uart0: serial@11002000 {
> +		compatible = "mediatek,mt6765-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11002000 0 0x400>;
> +		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&uart_clk>;
> +		status = "disabled";
> +	};

You need "baud" and "bus" clock. Also add clock-names please.

> +
> +	uart1: serial@11003000 {
> +		compatible = "mediatek,mt6765-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11003000 0 0x400>;
> +		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&uart_clk>;
> +		status = "disabled";

Same here obviously.

Regards,
Matthias

  parent reply	other threads:[~2018-06-15  8:54 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 22:40 Add basic SoC support for MT6765 Mars Cheng
2018-06-12 22:40 ` Mars Cheng
2018-06-12 22:40 ` [PATCH 1/2] ndings: mediatek: Add bindings for mediatek MT6765 Platform Mars Cheng
2018-06-12 22:40   ` Mars Cheng
2018-06-13  0:51   ` Rob Herring
2018-06-13  1:59     ` Mars Cheng
2018-06-13  1:59       ` Mars Cheng
2018-06-12 22:40 ` [PATCH 2/2] arm64: dts: mediatek: add mt6765 support Mars Cheng
2018-06-12 22:40   ` Mars Cheng
2018-06-13  0:58   ` Rob Herring
2018-06-13  1:56     ` Mars Cheng
2018-06-13  1:56       ` Mars Cheng
2018-06-15  8:54   ` Matthias Brugger [this message]
2018-06-20  0:18     ` Mars Cheng
2018-06-20  0:18       ` Mars Cheng

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