From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robin Murphy Subject: Re: [PATCH v16 5/5] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Date: Wed, 26 Sep 2018 16:59:09 +0100 Message-ID: <80f7a7df-9a6d-9de3-4c7c-261d96fb04e4@arm.com> References: <20180830144541.17740-1-vivek.gautam@codeaurora.org> <20180830144541.17740-6-vivek.gautam@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180830144541.17740-6-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Content-Language: en-GB List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: Vivek Gautam , joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, 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mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728442AbeIZWMu (ORCPT ); Wed, 26 Sep 2018 18:12:50 -0400 Received: from foss.arm.com ([217.140.101.70]:49094 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727280AbeIZWMu (ORCPT ); Wed, 26 Sep 2018 18:12:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B514F18A; Wed, 26 Sep 2018 08:59:13 -0700 (PDT) Received: from [10.4.12.131] (e110467-lin.emea.arm.com [10.4.12.131]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 864623F5BD; Wed, 26 Sep 2018 08:59:10 -0700 (PDT) Subject: Re: [PATCH v16 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant To: Vivek Gautam , joro@8bytes.org, robh+dt@kernel.org, will.deacon@arm.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: alex.williamson@redhat.com, mark.rutland@arm.com, rjw@rjwysocki.net, robdclark@gmail.com, linux-pm@vger.kernel.org, freedreno@lists.freedesktop.org, sboyd@kernel.org, tfiga@chromium.org, jcrouse@codeaurora.org, sricharan@codeaurora.org, m.szyprowski@samsung.com, architt@codeaurora.org, linux-arm-msm@vger.kernel.org References: <20180830144541.17740-1-vivek.gautam@codeaurora.org> <20180830144541.17740-6-vivek.gautam@codeaurora.org> From: Robin Murphy Message-ID: <80f7a7df-9a6d-9de3-4c7c-261d96fb04e4@arm.com> Date: Wed, 26 Sep 2018 16:59:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180830144541.17740-6-vivek.gautam@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/08/18 15:45, Vivek Gautam wrote: > qcom,smmu-v2 is an arm,smmu-v2 implementation with specific > clock and power requirements. > On msm8996, multiple cores, viz. mdss, video, etc. use this > smmu. On sdm845, this smmu is used with gpu. > Add bindings for the same. > > Signed-off-by: Vivek Gautam > Reviewed-by: Rob Herring > Reviewed-by: Tomasz Figa > Tested-by: Srinivas Kandagatla > --- > drivers/iommu/arm-smmu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index 166c8c6da24f..411e5ac57c64 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -119,6 +119,7 @@ enum arm_smmu_implementation { > GENERIC_SMMU, > ARM_MMU500, > CAVIUM_SMMUV2, > + QCOM_SMMUV2, Hmm, it seems we don't actually need this right now, but maybe that just means there's more imp-def registers and/or errata to come ;) Either way I guess there's no real harm in having it. Reviewed-by: Robin Murphy > }; > > struct arm_smmu_s2cr { > @@ -1970,6 +1971,17 @@ ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU); > ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500); > ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2); > > +static const char * const qcom_smmuv2_clks[] = { > + "bus", "iface", > +}; > + > +static const struct arm_smmu_match_data qcom_smmuv2 = { > + .version = ARM_SMMU_V2, > + .model = QCOM_SMMUV2, > + .clks = qcom_smmuv2_clks, > + .num_clks = ARRAY_SIZE(qcom_smmuv2_clks), > +}; > + > static const struct of_device_id arm_smmu_of_match[] = { > { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 }, > { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 }, > @@ -1977,6 +1989,7 @@ static const struct of_device_id arm_smmu_of_match[] = { > { .compatible = "arm,mmu-401", .data = &arm_mmu401 }, > { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, > { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, > + { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 }, > { }, > }; > MODULE_DEVICE_TABLE(of, arm_smmu_of_match); >