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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id o17sm14272edz.83.2020.03.05.00.58.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2020 00:58:17 -0800 (PST) Subject: Re: [PATCH v7 01/17] ppc: Remove stub support for 32-bit hypervisor mode To: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org, groug@kaod.org References: <20200303034351.333043-1-david@gibson.dropbear.id.au> <20200303034351.333043-2-david@gibson.dropbear.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <80ff6c03-68ed-be51-22b9-208ce3a52332@redhat.com> Date: Thu, 5 Mar 2020 09:58:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200303034351.333043-2-david@gibson.dropbear.id.au> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, farosas@linux.ibm.com, Mark Cave-Ayland , Igor Mammedov , paulus@samba.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/3/20 4:43 AM, David Gibson wrote: > a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not > fundamentally available only for PowerPC 64" and added a 32-bit version > of the MSR[HV] bit. >=20 > But nothing was ever really done with that; there is no meaningful suppor= t > for 32-bit hypervisor mode 13 years later. Let's stop pretending and jus= t > remove the stubs. >=20 > Signed-off-by: David Gibson > Reviewed-by: Fabiano Rosas > Reviewed-by: Greg Kurz > --- > target/ppc/cpu.h | 21 +++++++-------------- > target/ppc/translate_init.inc.c | 6 +++--- > 2 files changed, 10 insertions(+), 17 deletions(-) >=20 > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index b283042515..8077fdb068 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -24,8 +24,6 @@ > #include "exec/cpu-defs.h" > #include "cpu-qom.h" > =20 > -/* #define PPC_EMULATE_32BITS_HYPV */ > - > #define TCG_GUEST_DEFAULT_MO 0 > =20 > #define TARGET_PAGE_BITS_64K 16 > @@ -300,13 +298,12 @@ typedef struct ppc_v3_pate_t { > #define MSR_SF 63 /* Sixty-four-bit mode h= flags */ > #define MSR_TAG 62 /* Tag-active mode (POWERx ?) = */ > #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 = */ > -#define MSR_SHV 60 /* hypervisor state hf= lags */ > +#define MSR_HV 60 /* hypervisor state hf= lags */ > #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) = */ > #define MSR_TS1 33 > #define MSR_TM 32 /* Transactional Memory Available (Book3s) = */ > #define MSR_CM 31 /* Computation mode for BookE h= flags */ > #define MSR_ICM 30 /* Interrupt computation mode for BookE = */ > -#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hf= lags */ > #define MSR_GS 28 /* guest state for BookE = */ > #define MSR_UCLE 26 /* User-mode cache lock enable for BookE = */ > #define MSR_VR 25 /* altivec available x h= flags */ > @@ -401,10 +398,13 @@ typedef struct ppc_v3_pate_t { > =20 > #define msr_sf ((env->msr >> MSR_SF) & 1) > #define msr_isf ((env->msr >> MSR_ISF) & 1) > -#define msr_shv ((env->msr >> MSR_SHV) & 1) > +#if defined(TARGET_PPC64) > +#define msr_hv ((env->msr >> MSR_HV) & 1) > +#else > +#define msr_hv (0) > +#endif > #define msr_cm ((env->msr >> MSR_CM) & 1) > #define msr_icm ((env->msr >> MSR_ICM) & 1) > -#define msr_thv ((env->msr >> MSR_THV) & 1) > #define msr_gs ((env->msr >> MSR_GS) & 1) > #define msr_ucle ((env->msr >> MSR_UCLE) & 1) > #define msr_vr ((env->msr >> MSR_VR) & 1) > @@ -449,16 +449,9 @@ typedef struct ppc_v3_pate_t { > =20 > /* Hypervisor bit is more specific */ > #if defined(TARGET_PPC64) > -#define MSR_HVB (1ULL << MSR_SHV) > -#define msr_hv msr_shv > -#else > -#if defined(PPC_EMULATE_32BITS_HYPV) > -#define MSR_HVB (1ULL << MSR_THV) > -#define msr_hv msr_thv > +#define MSR_HVB (1ULL << MSR_HV) > #else > #define MSR_HVB (0ULL) > -#define msr_hv (0) > -#endif > #endif > =20 > /* DSISR */ > diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.= inc.c > index 2f7125c51f..df3401cf06 100644 > --- a/target/ppc/translate_init.inc.c > +++ b/target/ppc/translate_init.inc.c > @@ -8764,7 +8764,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > PPC2_TM | PPC2_PM_ISA206; > pcc->msr_mask =3D (1ull << MSR_SF) | > - (1ull << MSR_SHV) | > + (1ull << MSR_HV) | > (1ull << MSR_TM) | > (1ull << MSR_VR) | > (1ull << MSR_VSX) | > @@ -8976,7 +8976,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; > pcc->msr_mask =3D (1ull << MSR_SF) | > - (1ull << MSR_SHV) | > + (1ull << MSR_HV) | > (1ull << MSR_TM) | > (1ull << MSR_VR) | > (1ull << MSR_VSX) | > @@ -9186,7 +9186,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data= ) > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | > PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; > pcc->msr_mask =3D (1ull << MSR_SF) | > - (1ull << MSR_SHV) | > + (1ull << MSR_HV) | > (1ull << MSR_TM) | > (1ull << MSR_VR) | > (1ull << MSR_VSX) | >=20 Reviewed-by: Philippe Mathieu-Daud=E9