From mboxrd@z Thu Jan  1 00:00:00 1970
From: Patrice CHOTARD <patrice.chotard@st.com>
Date: Tue, 31 Mar 2020 08:35:16 +0000
Subject: [PATCH V2 09/14] ARM: dts: stm32: Add alternate pinmux for
 ethernet RGMII
In-Reply-To: <20200331004851.282583-10-marex@denx.de>
References: <20200331004851.282583-1-marex@denx.de>
 <20200331004851.282583-10-marex@denx.de>
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To: u-boot@lists.denx.de

Hi Marek

On 3/31/20 2:48 AM, Marek Vasut wrote:
> Add another mux option for DWMAC RGMII, this is used on AV96 board.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> Cc: Patrice Chotard <patrice.chotard@st.com>


Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

Thanks

> ---
> V2: No change
> ---
>  arch/arm/dts/stm32mp157-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
> index 964e4910ec..422dad1ddd 100644
> --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
> @@ -288,6 +288,57 @@
>  				};
>  			};
>  
> +			ethernet0_rgmii_pins_b: rgmii-1 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
> +						 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
> +						 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
> +						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
> +						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
> +						 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
> +						 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
> +						 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <2>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <0>;
> +				};
> +				pins3 {
> +					pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
> +						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
> +						 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
> +						 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
> +						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
> +						 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
> +					bias-disable;
> +				};
> +			};
> +
> +			ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
> +						 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
> +						 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
> +						 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
> +						 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
> +						 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
> +						 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
> +						 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
> +						 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
> +						 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
> +						 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
> +						 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
> +						 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
> +						 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
> +						 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
> +				};
> +			};
> +
>  			fmc_pins_a: fmc-0 {
>  				pins1 {
>  					pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */