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From: "Bean Huo (beanhuo)" <beanhuo@micron.com>
To: Boris Brezillon <boris.brezillon@bootlin.com>
CC: Richard Weinberger <richard@nod.at>, Miquel Raynal
 <miquel.raynal@bootlin.com>, "linux-mtd@lists.infradead.org"
 <linux-mtd@lists.infradead.org>, Chris Packham
 <chris.packham@alliedtelesis.co.nz>, David Woodhouse <dwmw2@infradead.org>,
 Brian Norris <computersforpeace@gmail.com>, Marek Vasut
 <marek.vasut@gmail.com>
Subject: RE: [EXT] Re:  [PATCH 2/2] mtd: rawnand: micron: Fix on-die ECC
 detection logic
Date: Thu, 12 Jul 2018 08:40:33 +0000
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 <20180711123209.5271d411@bbrezillon>
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Hi, Boris
It is true. Bit7 of byte4 in READID changes after enable/disable internal E=
CC in case of  its default value is 0.=20
Also this bit value  is volatile. After power cyling, it resets to default =
value. I don't know if
this condition will be changed or kept since maybe it was a specific design=
 request from customers.
But GET Feature is still the preferred way to determine the state of ECC, w=
e recommend using this way.=20
If internal ECC is default on, we don't do anything, and if default is off,=
 then SET feature and GET feature.
This always makes sense.

I am still digging into why this doesn't depict in datasheet and whether th=
is will be kept in coming design.
As long I have new update, I will back to you.

>
>That's not what the board I have on my desk says. I have a
>MT29F2G08ABAEAH4, and I can tell you for sure this bit changes when I
>enable/disable on-die ECC. Do the test, and you'll see...
>
>See, that's what I'm complaining about. You keep saying things that appear=
 to
>be untrue when when we check on real HW parts. So, either we have NANDs
>that are buggy, or you didn't check yourself.
>
>Regards,
>
>Boris