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Tue, 24 Jan 2023 04:24:50 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id k16-20020a7bc410000000b003d99469ece1sm13200111wmi.24.2023.01.24.04.24.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 04:24:50 -0800 (PST) Message-ID: <81f80190-a05c-5d0d-11b2-a80573b86e1c@linaro.org> Date: Tue, 24 Jan 2023 13:24:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v3 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Content-Language: en-US To: Herve Codina Cc: Li Yang , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-6-herve.codina@bootlin.com> <316ddb81-8d13-71dd-3396-412e31cfb880@linaro.org> <20230124104232.183cc9ff@bootlin.com> <37a95380-ee68-5c3a-3b96-48cc8b525f19@linaro.org> <20230124122347.1a531d0f@bootlin.com> From: Krzysztof Kozlowski In-Reply-To: <20230124122347.1a531d0f@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24/01/2023 12:23, Herve Codina wrote: > On Tue, 24 Jan 2023 11:02:52 +0100 > Krzysztof Kozlowski wrote: > >> On 24/01/2023 10:42, Herve Codina wrote: >>> Hi Krzysztof, >>> >>> On Tue, 17 Jan 2023 12:31:09 +0100 >>> Krzysztof Kozlowski wrote: >>> >>>> On 13/01/2023 11:37, Herve Codina wrote: >>>>> Add support for the QMC (QUICC Multichannel Controller) >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>>>> >>>>> Signed-off-by: Herve Codina >>>>> --- >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>>>> 1 file changed, 164 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3ec52f1635c8 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> @@ -0,0 +1,164 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>>>> + >>>>> +maintainers: >>>>> + - Herve Codina >>>>> + >>>>> +description: | >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>>>> + one serial controller using the same TDM physical interface routed from >>>>> + TSA. >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>>> + - fsl,mpc885-scc-qmc >>>>> + - fsl,mpc866-scc-qmc >>>>> + - const: fsl,cpm1-scc-qmc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: SCC (Serial communication controller) register base >>>>> + - description: SCC parameter ram base >>>>> + - description: Dual port ram base >>>>> + >>>>> + reg-names: >>>>> + items: >>>>> + - const: scc_regs >>>>> + - const: scc_pram >>>>> + - const: dpram >>>>> + >>>>> + interrupts: >>>>> + maxItems: 1 >>>>> + description: SCC interrupt line in the CPM interrupt controller >>>>> + >>>>> + fsl,tsa: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle to the TSA >>>>> + >>>>> + fsl,tsa-cell-id: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: [1, 2, 3] >>>>> + description: | >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>>>> + - 1: SCC2 >>>>> + - 2: SCC3 >>>>> + - 3: SCC4 >>>> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa >>>> property, just like we do for all syscon-like phandles. >>> >>> Yes, indeed. >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number >>> pair (the phandle to TSA node and the TSA cell id to use) >> >> Move to fsl,tsa, not from. > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > fsl,tsa-cell: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - items: > - description: phandle to TSA node > - enum: [1, 2, 3] > description: | > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > - 1: SCC2 > - 2: SCC3 > - 3: SCC4 > description: > Should be a phandle/number pair. The phandle to TSA node and the TSA > cell ID to use. > > Is that what you were thinking about ? Yes, except again, so third time, why calling this "cell"? Move it to fsl,tsa. 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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v3 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Content-Language: en-US To: Herve Codina References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-6-herve.codina@bootlin.com> <316ddb81-8d13-71dd-3396-412e31cfb880@linaro.org> <20230124104232.183cc9ff@bootlin.com> <37a95380-ee68-5c3a-3b96-48cc8b525f19@linaro.org> <20230124122347.1a531d0f@bootlin.com> From: Krzysztof Kozlowski In-Reply-To: <20230124122347.1a531d0f@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Michael Ellerman , Takashi Iwai , Nicholas Piggin , Liam Girdwood , Rob Herring , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Christophe Leroy , Krzysztof Kozlowski , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On 24/01/2023 12:23, Herve Codina wrote: > On Tue, 24 Jan 2023 11:02:52 +0100 > Krzysztof Kozlowski wrote: > >> On 24/01/2023 10:42, Herve Codina wrote: >>> Hi Krzysztof, >>> >>> On Tue, 17 Jan 2023 12:31:09 +0100 >>> Krzysztof Kozlowski wrote: >>> >>>> On 13/01/2023 11:37, Herve Codina wrote: >>>>> Add support for the QMC (QUICC Multichannel Controller) >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>>>> >>>>> Signed-off-by: Herve Codina >>>>> --- >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>>>> 1 file changed, 164 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3ec52f1635c8 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> @@ -0,0 +1,164 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>>>> + >>>>> +maintainers: >>>>> + - Herve Codina >>>>> + >>>>> +description: | >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>>>> + one serial controller using the same TDM physical interface routed from >>>>> + TSA. >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>>> + - fsl,mpc885-scc-qmc >>>>> + - fsl,mpc866-scc-qmc >>>>> + - const: fsl,cpm1-scc-qmc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: SCC (Serial communication controller) register base >>>>> + - description: SCC parameter ram base >>>>> + - description: Dual port ram base >>>>> + >>>>> + reg-names: >>>>> + items: >>>>> + - const: scc_regs >>>>> + - const: scc_pram >>>>> + - const: dpram >>>>> + >>>>> + interrupts: >>>>> + maxItems: 1 >>>>> + description: SCC interrupt line in the CPM interrupt controller >>>>> + >>>>> + fsl,tsa: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle to the TSA >>>>> + >>>>> + fsl,tsa-cell-id: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: [1, 2, 3] >>>>> + description: | >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>>>> + - 1: SCC2 >>>>> + - 2: SCC3 >>>>> + - 3: SCC4 >>>> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa >>>> property, just like we do for all syscon-like phandles. >>> >>> Yes, indeed. >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number >>> pair (the phandle to TSA node and the TSA cell id to use) >> >> Move to fsl,tsa, not from. > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > fsl,tsa-cell: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - items: > - description: phandle to TSA node > - enum: [1, 2, 3] > description: | > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > - 1: SCC2 > - 2: SCC3 > - 3: SCC4 > description: > Should be a phandle/number pair. The phandle to TSA node and the TSA > cell ID to use. > > Is that what you were thinking about ? Yes, except again, so third time, why calling this "cell"? Move it to fsl,tsa. Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8407C25B4E for ; Tue, 24 Jan 2023 12:25:52 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4P1R5V73zHz3cf6 for ; Tue, 24 Jan 2023 23:25:50 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=yshX5LVf; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linaro.org (client-ip=2a00:1450:4864:20::32e; helo=mail-wm1-x32e.google.com; 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Tue, 24 Jan 2023 04:24:50 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id k16-20020a7bc410000000b003d99469ece1sm13200111wmi.24.2023.01.24.04.24.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 04:24:50 -0800 (PST) Message-ID: <81f80190-a05c-5d0d-11b2-a80573b86e1c@linaro.org> Date: Tue, 24 Jan 2023 13:24:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v3 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Content-Language: en-US To: Herve Codina References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-6-herve.codina@bootlin.com> <316ddb81-8d13-71dd-3396-412e31cfb880@linaro.org> <20230124104232.183cc9ff@bootlin.com> <37a95380-ee68-5c3a-3b96-48cc8b525f19@linaro.org> <20230124122347.1a531d0f@bootlin.com> From: Krzysztof Kozlowski In-Reply-To: <20230124122347.1a531d0f@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Takashi Iwai , Nicholas Piggin , Liam Girdwood , Rob Herring , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Krzysztof Kozlowski , Jaroslav Kysela , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 24/01/2023 12:23, Herve Codina wrote: > On Tue, 24 Jan 2023 11:02:52 +0100 > Krzysztof Kozlowski wrote: > >> On 24/01/2023 10:42, Herve Codina wrote: >>> Hi Krzysztof, >>> >>> On Tue, 17 Jan 2023 12:31:09 +0100 >>> Krzysztof Kozlowski wrote: >>> >>>> On 13/01/2023 11:37, Herve Codina wrote: >>>>> Add support for the QMC (QUICC Multichannel Controller) >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>>>> >>>>> Signed-off-by: Herve Codina >>>>> --- >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>>>> 1 file changed, 164 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3ec52f1635c8 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> @@ -0,0 +1,164 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>>>> + >>>>> +maintainers: >>>>> + - Herve Codina >>>>> + >>>>> +description: | >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>>>> + one serial controller using the same TDM physical interface routed from >>>>> + TSA. >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>>> + - fsl,mpc885-scc-qmc >>>>> + - fsl,mpc866-scc-qmc >>>>> + - const: fsl,cpm1-scc-qmc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: SCC (Serial communication controller) register base >>>>> + - description: SCC parameter ram base >>>>> + - description: Dual port ram base >>>>> + >>>>> + reg-names: >>>>> + items: >>>>> + - const: scc_regs >>>>> + - const: scc_pram >>>>> + - const: dpram >>>>> + >>>>> + interrupts: >>>>> + maxItems: 1 >>>>> + description: SCC interrupt line in the CPM interrupt controller >>>>> + >>>>> + fsl,tsa: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle to the TSA >>>>> + >>>>> + fsl,tsa-cell-id: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: [1, 2, 3] >>>>> + description: | >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>>>> + - 1: SCC2 >>>>> + - 2: SCC3 >>>>> + - 3: SCC4 >>>> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa >>>> property, just like we do for all syscon-like phandles. >>> >>> Yes, indeed. >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number >>> pair (the phandle to TSA node and the TSA cell id to use) >> >> Move to fsl,tsa, not from. > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > fsl,tsa-cell: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - items: > - description: phandle to TSA node > - enum: [1, 2, 3] > description: | > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > - 1: SCC2 > - 2: SCC3 > - 3: SCC4 > description: > Should be a phandle/number pair. The phandle to TSA node and the TSA > cell ID to use. > > Is that what you were thinking about ? Yes, except again, so third time, why calling this "cell"? Move it to fsl,tsa. Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0C91C25B4E for ; Tue, 24 Jan 2023 12:25:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+abpNUoCR+9NFXPpNoJ1TztYSN0xYdnKiL1S15oECrE=; b=iOrYxEW0zNZNjw i1YCZ8YOUAg+ISUn0TwU1JDxvt5a2VU0jY9myPrwRER8KKxrm/jMxfS1UE2iWCoFhbZsMI/8XwKt0 8lGigk0ytsJB8s+Yr70Q9bPcDGfTDnsk9GqklnSIT1PFl/eCc6cRd2FXJMbdBYqtJsyVjktBQwD5a nmUN91wLofp2iKFgYG1WzEY5j041HsNBViymHEPIQ9aHNCWuo2zVoi4iAUW73xB20RYoc9xQHpqjq 7U51iLImFDW3CUwI5PhKdKejYu7O8QIbd9hehfDCplk8bqWxFnHYa1fclpTMiGGLB7XrR0rkItRtM gKsSZAF1t1NLI5+Xl7fQ==; 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Tue, 24 Jan 2023 04:24:50 -0800 (PST) Message-ID: <81f80190-a05c-5d0d-11b2-a80573b86e1c@linaro.org> Date: Tue, 24 Jan 2023 13:24:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v3 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Content-Language: en-US To: Herve Codina Cc: Li Yang , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-6-herve.codina@bootlin.com> <316ddb81-8d13-71dd-3396-412e31cfb880@linaro.org> <20230124104232.183cc9ff@bootlin.com> <37a95380-ee68-5c3a-3b96-48cc8b525f19@linaro.org> <20230124122347.1a531d0f@bootlin.com> From: Krzysztof Kozlowski In-Reply-To: <20230124122347.1a531d0f@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230124_042454_840959_1F58B403 X-CRM114-Status: GOOD ( 19.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/01/2023 12:23, Herve Codina wrote: > On Tue, 24 Jan 2023 11:02:52 +0100 > Krzysztof Kozlowski wrote: > >> On 24/01/2023 10:42, Herve Codina wrote: >>> Hi Krzysztof, >>> >>> On Tue, 17 Jan 2023 12:31:09 +0100 >>> Krzysztof Kozlowski wrote: >>> >>>> On 13/01/2023 11:37, Herve Codina wrote: >>>>> Add support for the QMC (QUICC Multichannel Controller) >>>>> available in some PowerQUICC SoC such as MPC885 or MPC866. >>>>> >>>>> Signed-off-by: Herve Codina >>>>> --- >>>>> .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 164 ++++++++++++++++++ >>>>> 1 file changed, 164 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..3ec52f1635c8 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml >>>>> @@ -0,0 +1,164 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) >>>>> + >>>>> +maintainers: >>>>> + - Herve Codina >>>>> + >>>>> +description: | >>>>> + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within >>>>> + one serial controller using the same TDM physical interface routed from >>>>> + TSA. >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + items: >>>>> + - enum: >>>>> + - fsl,mpc885-scc-qmc >>>>> + - fsl,mpc866-scc-qmc >>>>> + - const: fsl,cpm1-scc-qmc >>>>> + >>>>> + reg: >>>>> + items: >>>>> + - description: SCC (Serial communication controller) register base >>>>> + - description: SCC parameter ram base >>>>> + - description: Dual port ram base >>>>> + >>>>> + reg-names: >>>>> + items: >>>>> + - const: scc_regs >>>>> + - const: scc_pram >>>>> + - const: dpram >>>>> + >>>>> + interrupts: >>>>> + maxItems: 1 >>>>> + description: SCC interrupt line in the CPM interrupt controller >>>>> + >>>>> + fsl,tsa: >>>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>>> + description: phandle to the TSA >>>>> + >>>>> + fsl,tsa-cell-id: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: [1, 2, 3] >>>>> + description: | >>>>> + TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) >>>>> + - 1: SCC2 >>>>> + - 2: SCC3 >>>>> + - 3: SCC4 >>>> >>>> Is this used as argument to tsa? If so, this should be part of fsl,tsa >>>> property, just like we do for all syscon-like phandles. >>> >>> Yes, indeed. >>> I will move 'fsl,tsa' to 'fsl,tsa-cell' with 'fsl,tsa-cell' a phandle/number >>> pair (the phandle to TSA node and the TSA cell id to use) >> >> Move to fsl,tsa, not from. > > Well, I plan to remove both fsl,tsa and fsl,tsa-cell-id and use this: > fsl,tsa-cell: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - items: > - description: phandle to TSA node > - enum: [1, 2, 3] > description: | > TSA cell ID (dt-bindings/soc/fsl,tsa.h defines these values) > - 1: SCC2 > - 2: SCC3 > - 3: SCC4 > description: > Should be a phandle/number pair. The phandle to TSA node and the TSA > cell ID to use. > > Is that what you were thinking about ? Yes, except again, so third time, why calling this "cell"? Move it to fsl,tsa. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel