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from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 6 Jun 2018 23:50:53 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.82]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.87]) with mapi id 14.03.0319.002; Thu, 7 Jun 2018 14:50:51 +0800 From: "Kang, Luwei" To: "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "peterz@infradead.org" , "alexander.shishkin@linux.intel.com" , "hpa@zytor.com" CC: "x86@kernel.org" , "chao.p.peng@linux.intel.com" , "thomas.lendacky@amd.com" , "bp@suse.de" , "Liang, Kan" , "Janakarajan.Natarajan@amd.com" , "dwmw@amazon.co.uk" , "linux-kernel@vger.kernel.org" , "mathieu.poirier@linaro.org" , "kstewart@linuxfoundation.org" , "gregkh@linuxfoundation.org" , "rkrcmar@redhat.com" , "david@redhat.com" , "bsd@redhat.com" , "yu.c.zhang@linux.intel.com" , "joro@8bytes.org" Subject: RE: [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Thread-Topic: [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header Thread-Index: AQHT8XiywMAZxFSpsEGuxZJAkMIGbaRUcLog Date: Thu, 7 Jun 2018 06:50:50 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FE8E4B@SHSMSX101.ccr.corp.intel.com> References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com> <1526964735-16566-2-git-send-email-luwei.kang@intel.com> In-Reply-To: <1526964735-16566-2-git-send-email-luwei.kang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZGNiOTlmMWQtNmIyNS00MGMzLTg0YzktNjNkODczYzdjNTU5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWWJsanpvS1RpamhYb3lWcFJwcHNEVHlIRjFjcFwvMjhcL3BcLzhENFRiUFg0SmxXNjJHSUVMbWsxaEZwNTV2bWF3MCJ9 dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Kang, Luwei > Sent: Tuesday, May 22, 2018 12:52 PM > To: kvm@vger.kernel.org > Cc: tglx@linutronix.de; mingo@redhat.com; hpa@zytor.com; x86@kernel.org; chao.p.peng@linux.intel.com; > thomas.lendacky@amd.com; bp@suse.de; Liang, Kan ; Janakarajan.Natarajan@amd.com; > dwmw@amazon.co.uk; linux-kernel@vger.kernel.org; alexander.shishkin@linux.intel.com; peterz@infradead.org; > mathieu.poirier@linaro.org; kstewart@linuxfoundation.org; gregkh@linuxfoundation.org; pbonzini@redhat.com; > rkrcmar@redhat.com; david@redhat.com; bsd@redhat.com; yu.c.zhang@linux.intel.com; joro@8bytes.org; Kang, Luwei > > Subject: [PATCH v9 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit definitions to a public header > > From: Chao Peng > > Intel Processor Trace virtualization enabling in KVM guest need to access these MSRs bit definitions, so move them to public header > file msr-index.h. > > Signed-off-by: Chao Peng > Signed-off-by: Luwei Kang > --- > arch/x86/events/intel/pt.h | 37 ------------------------------------- > arch/x86/include/asm/msr-index.h | 33 +++++++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+), 37 deletions(-) > > diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h index 0eb41d0..0050ca1 100644 > --- a/arch/x86/events/intel/pt.h > +++ b/arch/x86/events/intel/pt.h > @@ -20,43 +20,6 @@ > #define __INTEL_PT_H__ > > /* > - * PT MSR bit definitions > - */ > -#define RTIT_CTL_TRACEEN BIT(0) > -#define RTIT_CTL_CYCLEACC BIT(1) > -#define RTIT_CTL_OS BIT(2) > -#define RTIT_CTL_USR BIT(3) > -#define RTIT_CTL_PWR_EVT_EN BIT(4) > -#define RTIT_CTL_FUP_ON_PTW BIT(5) > -#define RTIT_CTL_CR3EN BIT(7) > -#define RTIT_CTL_TOPA BIT(8) > -#define RTIT_CTL_MTC_EN BIT(9) > -#define RTIT_CTL_TSC_EN BIT(10) > -#define RTIT_CTL_DISRETC BIT(11) > -#define RTIT_CTL_PTW_EN BIT(12) > -#define RTIT_CTL_BRANCH_EN BIT(13) > -#define RTIT_CTL_MTC_RANGE_OFFSET 14 > -#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) > -#define RTIT_CTL_CYC_THRESH_OFFSET 19 > -#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) > -#define RTIT_CTL_PSB_FREQ_OFFSET 24 > -#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) > -#define RTIT_CTL_ADDR0_OFFSET 32 > -#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) > -#define RTIT_CTL_ADDR1_OFFSET 36 > -#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) > -#define RTIT_CTL_ADDR2_OFFSET 40 > -#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) > -#define RTIT_CTL_ADDR3_OFFSET 44 > -#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) > -#define RTIT_STATUS_FILTEREN BIT(0) > -#define RTIT_STATUS_CONTEXTEN BIT(1) > -#define RTIT_STATUS_TRIGGEREN BIT(2) > -#define RTIT_STATUS_BUFFOVF BIT(3) > -#define RTIT_STATUS_ERROR BIT(4) > -#define RTIT_STATUS_STOPPED BIT(5) > - > -/* > * Single-entry ToPA: when this close to region boundary, switch > * buffers to avoid losing data. > */ > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 53d5b1b..afe4e13 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -106,7 +106,40 @@ > #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 > > #define MSR_IA32_RTIT_CTL 0x00000570 > +#define RTIT_CTL_TRACEEN BIT(0) > +#define RTIT_CTL_CYCLEACC BIT(1) > +#define RTIT_CTL_OS BIT(2) > +#define RTIT_CTL_USR BIT(3) > +#define RTIT_CTL_PWR_EVT_EN BIT(4) > +#define RTIT_CTL_FUP_ON_PTW BIT(5) > +#define RTIT_CTL_CR3EN BIT(7) > +#define RTIT_CTL_TOPA BIT(8) > +#define RTIT_CTL_MTC_EN BIT(9) > +#define RTIT_CTL_TSC_EN BIT(10) > +#define RTIT_CTL_DISRETC BIT(11) > +#define RTIT_CTL_PTW_EN BIT(12) > +#define RTIT_CTL_BRANCH_EN BIT(13) > +#define RTIT_CTL_MTC_RANGE_OFFSET 14 > +#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) > +#define RTIT_CTL_CYC_THRESH_OFFSET 19 > +#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) > +#define RTIT_CTL_PSB_FREQ_OFFSET 24 > +#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) > +#define RTIT_CTL_ADDR0_OFFSET 32 > +#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) > +#define RTIT_CTL_ADDR1_OFFSET 36 > +#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) > +#define RTIT_CTL_ADDR2_OFFSET 40 > +#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) > +#define RTIT_CTL_ADDR3_OFFSET 44 > +#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) > #define MSR_IA32_RTIT_STATUS 0x00000571 > +#define RTIT_STATUS_FILTEREN BIT(0) > +#define RTIT_STATUS_CONTEXTEN BIT(1) > +#define RTIT_STATUS_TRIGGEREN BIT(2) > +#define RTIT_STATUS_BUFFOVF BIT(3) > +#define RTIT_STATUS_ERROR BIT(4) > +#define RTIT_STATUS_STOPPED BIT(5) > #define MSR_IA32_RTIT_ADDR0_A 0x00000580 > #define MSR_IA32_RTIT_ADDR0_B 0x00000581 > #define MSR_IA32_RTIT_ADDR1_A 0x00000582 Hi, Patch 1~5 have some code changes in x86 native for Intel Processor Trace virtualization enabling in KVM guest. I have sent patch set v9 which include some minor changes from old version. Do you have any comments? Thanks, Luwei Kang