From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org by pdx-caf-mail.web.codeaurora.org (Dovecot) with LMTP id NrRZDKSRGltsaAAAmS7hNA ; Fri, 08 Jun 2018 14:26:18 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 33889607E4; Fri, 8 Jun 2018 14:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham autolearn_force=no version=3.4.0 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by smtp.codeaurora.org (Postfix) with ESMTP id C22E1607A4; Fri, 8 Jun 2018 14:26:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C22E1607A4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752734AbeFHO0O convert rfc822-to-8bit (ORCPT + 25 others); Fri, 8 Jun 2018 10:26:14 -0400 Received: from mga12.intel.com ([192.55.52.136]:15738 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752459AbeFHO0M (ORCPT ); Fri, 8 Jun 2018 10:26:12 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jun 2018 07:26:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,490,1520924400"; d="scan'208";a="235528157" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga005.fm.intel.com with ESMTP; 08 Jun 2018 07:26:11 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 8 Jun 2018 07:26:11 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.82]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.51]) with mapi id 14.03.0319.002; Fri, 8 Jun 2018 22:26:10 +0800 From: "Kang, Luwei" To: Alexander Shishkin CC: "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "chao.p.peng@linux.intel.com" , "thomas.lendacky@amd.com" , "bp@suse.de" , "Liang, Kan" , "Janakarajan.Natarajan@amd.com" , "dwmw@amazon.co.uk" , "linux-kernel@vger.kernel.org" , "peterz@infradead.org" , "mathieu.poirier@linaro.org" , "kstewart@linuxfoundation.org" , "gregkh@linuxfoundation.org" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "david@redhat.com" , "bsd@redhat.com" , "yu.c.zhang@linux.intel.com" , "joro@8bytes.org" Subject: RE: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Thread-Topic: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Thread-Index: AQHT8Xi40DWVm7BbrE+rqN9Qj2UB8qRUXxQAgAImVjA= Date: Fri, 8 Jun 2018 14:26:08 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FEFFF6@SHSMSX101.ccr.corp.intel.com> References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com> <1526964735-16566-4-git-send-email-luwei.kang@intel.com> <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> In-Reply-To: <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > These bit definitions are use for emulate MSRs read/write for KVM. For > > example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when > > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this > > bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected > > to KVM guest. > > Do we have anything in the guest that this feature will work with? > It depend on PT driver. KVM need to do some security check if kvm guest (maybe linux or other os) try to set any bits of these MSRs. Thanks, Luwei Kang From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kang, Luwei" Subject: RE: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs Date: Fri, 8 Jun 2018 14:26:08 +0000 Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FEFFF6@SHSMSX101.ccr.corp.intel.com> References: <1526964735-16566-1-git-send-email-luwei.kang@intel.com> <1526964735-16566-4-git-send-email-luwei.kang@intel.com> <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Cc: "kvm@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "x86@kernel.org" , "chao.p.peng@linux.intel.com" , "thomas.lendacky@amd.com" , "bp@suse.de" , "Liang, Kan" , "Janakarajan.Natarajan@amd.com" , "dwmw@amazon.co.uk" , "linux-kernel@vger.kernel.org" , "peterz@infradead.org" , "mathieu.poirier@linaro.org" , "kstewart@linuxfoundation.org" , "gregkh@linuxfoundation.org" , "pbonzini@redha To: Alexander Shishkin Return-path: In-Reply-To: <20180607133306.vcrtxidfzv7x7e73@um.fi.intel.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org > > These bit definitions are use for emulate MSRs read/write for KVM. For > > example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when > > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this > > bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected > > to KVM guest. > > Do we have anything in the guest that this feature will work with? > It depend on PT driver. KVM need to do some security check if kvm guest (maybe linux or other os) try to set any bits of these MSRs. Thanks, Luwei Kang