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(p200300faaf0bb20074734860dc6c494f.dip0.t-ipconnect.de. [2003:fa:af0b:b200:7473:4860:dc6c:494f]) by smtp.gmail.com with ESMTPSA id a3-20020aa7cf03000000b0049019b48373sm3963266edy.85.2023.01.09.09.33.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 09:33:54 -0800 (PST) Date: Mon, 09 Jan 2023 17:33:49 +0000 From: Bernhard Beschow To: =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= , Mark Cave-Ayland , qemu-devel@nongnu.org CC: Eduardo Habkost , qemu-block@nongnu.org, =?ISO-8859-1?Q?Herv=E9_Poussineau?= , Ani Sinha , Richard Henderson , Jiaxun Yang , Aurelien Jarno , "Michael S. Tsirkin" , Paolo Bonzini , Igor Mammedov , Marcel Apfelbaum , John Snow , Gerd Hoffmann , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: Re: [PATCH v5 00/31] Consolidate PIIX south bridges In-Reply-To: <7f47fd16-8e87-32d0-9ae5-4b288930c24f@linaro.org> References: <20230105143228.244965-1-shentey@gmail.com> <50FFD7E4-A40C-4428-ACD2-F7C93C687572@gmail.com> <7f47fd16-8e87-32d0-9ae5-4b288930c24f@linaro.org> Message-ID: <82E6442C-A4A7-4287-98FF-DBCF99E68BEE@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 8=2E Januar 2023 18:28:28 UTC schrieb "Philippe Mathieu-Daud=C3=A9" : >On 8/1/23 16:12, Bernhard Beschow wrote: >> Am 7=2E Januar 2023 23:57:32 UTC schrieb Mark Cave-Ayland : >>> On 05/01/2023 14:31, Bernhard Beschow wrote: > >>>> Bernhard Beschow (28): >>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>> hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is >>>> created >>>> hw/i386/pc_piix: Allow for setting properties before realizing PI= IX3 >>>> south bridge >>>> hw/i386/pc: Create RTC controllers in south bridges >>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>> hw/isa/piix3: Create USB controller in host device >>>> hw/isa/piix3: Create power management controller in host device >>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>> hw/intc/i8259: Introduce i8259 proxy "isa-pic" >>>> hw/isa/piix3: Create ISA PIC in host device >>>> hw/isa/piix3: Create IDE controller in host device >>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>> hw/isa/piix4: Use ISA PIC device >>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>> hw/isa/piix3: Merge hw/isa/piix4=2Ec >>>> hw/isa/piix: Harmonize names of reset control memory regions >>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>> hw/isa/piix: Rename functions to be shared for interrupt triggeri= ng >>>> hw/isa/piix: Consolidate IRQ triggering >>>> hw/isa/piix: Share PIIX3's base class with PIIX4 > >>> Phil - over to you! > >Thanks for the review Mark! > >> Shall I respin? I could integrate my PCI series into this one in order = to avoid the outdated MIPS patches while still delivering a working series= =2E Yes/No? > >If you don't mind, that is certainly easier for me :) v6 is out! I've also rebased onto latest master which resolves some merge = conflicts (PCI, building) for you=2E I hope you don't mind some minor clean= ups that I've made to the PCI INTx series which aligns board code with my l= atest fuloong2e cleanup series=2E Best regards, Bernhard >