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Message-ID: <82caa10262d24c7484dd8caaff28c7d547858c43.camel@gmail.com>
Subject: Re: [PATCH 07/17] powerpc/qspinlock: store owner CPU in lock word
From: Jordan Niethe <jniethe5@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Date: Fri, 12 Aug 2022 10:50:12 +1000
In-Reply-To: <20220728063120.2867508-9-npiggin@gmail.com>
References: <20220728063120.2867508-1-npiggin@gmail.com>
	 <20220728063120.2867508-9-npiggin@gmail.com>
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On Thu, 2022-07-28 at 16:31 +-1000, Nicholas Piggin wrote:
+AD4 Store the owner CPU number in the lock word so it may be yielded to,
+AD4 as powerpc's paravirtualised simple spinlocks do.
+AD4 ---
+AD4  arch/powerpc/include/asm/qspinlock.h       +AHw  8 +-+-+-+-+-+-+--
+AD4  arch/powerpc/include/asm/qspinlock+AF8-types.h +AHw 10 +-+-+-+-+-+-+-+-+-+-
+AD4  arch/powerpc/lib/qspinlock.c               +AHw  6 +-+-+----
+AD4  3 files changed, 20 insertions(+-), 4 deletions(-)
+AD4 
+AD4 diff --git a/arch/powerpc/include/asm/qspinlock.h b/arch/powerpc/include/asm/qspinlock.h
+AD4 index 3ab354159e5e..44601b261e08 100644
+AD4 --- a/arch/powerpc/include/asm/qspinlock.h
+AD4 +-+-+- b/arch/powerpc/include/asm/qspinlock.h
+AD4 +AEAAQA -20,9 +-20,15 +AEAAQA static +AF8AXw-always+AF8-inline int queued+AF8-spin+AF8-is+AF8-contended(struct qspinlock +ACo-lock)
+AD4  	return +ACEAIQ(READ+AF8-ONCE(lock-+AD4-val) +ACY +AF8-Q+AF8-TAIL+AF8-CPU+AF8-MASK)+ADs
+AD4  +AH0
+AD4  
+AD4 +-static +AF8AXw-always+AF8-inline u32 queued+AF8-spin+AF8-get+AF8-locked+AF8-val(void)

Maybe this function should have +ACI-encode+ACI in the name to match with
encode+AF8-tail+AF8-cpu().


+AD4 +-+AHs
+AD4 +-	/+ACo XXX: make this use lock value in paca like simple spinlocks? +ACo-/

Is that the paca's lock+AF8-token which is 0x8000?


+AD4 +-	return +AF8-Q+AF8-LOCKED+AF8-VAL +AHw (smp+AF8-processor+AF8-id() +ADwAPA +AF8-Q+AF8-OWNER+AF8-CPU+AF8-OFFSET)+ADs
+AD4 +-+AH0
+AD4 +-
+AD4  static +AF8AXw-always+AF8-inline int queued+AF8-spin+AF8-trylock(struct qspinlock +ACo-lock)
+AD4  +AHs
+AD4 -	u32 new +AD0 +AF8-Q+AF8-LOCKED+AF8-VAL+ADs
+AD4 +-	u32 new +AD0 queued+AF8-spin+AF8-get+AF8-locked+AF8-val()+ADs
+AD4  	u32 prev+ADs
+AD4  
+AD4  	asm volatile(
+AD4 diff --git a/arch/powerpc/include/asm/qspinlock+AF8-types.h b/arch/powerpc/include/asm/qspinlock+AF8-types.h
+AD4 index 8b20f5e22bba..35f9525381e6 100644
+AD4 --- a/arch/powerpc/include/asm/qspinlock+AF8-types.h
+AD4 +-+-+- b/arch/powerpc/include/asm/qspinlock+AF8-types.h
+AD4 +AEAAQA -29,6 +-29,8 +AEAAQA typedef struct qspinlock +AHs
+AD4   +ACo Bitfields in the lock word:
+AD4   +ACo
+AD4   +ACo     0: locked bit
+AD4 +- +ACo  1-14: lock holder cpu
+AD4 +- +ACo    15: unused bit
+AD4   +ACo    16: must queue bit
+AD4   +ACo 17-31: tail cpu (+-1)

So there is one more bit to store the tail cpu vs the lock holder cpu?

+AD4   +ACo-/
+AD4 +AEAAQA -39,6 +-41,14 +AEAAQA typedef struct qspinlock +AHs
+AD4  +ACM-define +AF8-Q+AF8-LOCKED+AF8-MASK		+AF8-Q+AF8-SET+AF8-MASK(LOCKED)
+AD4  +ACM-define +AF8-Q+AF8-LOCKED+AF8-VAL		(1U +ADwAPA +AF8-Q+AF8-LOCKED+AF8-OFFSET)
+AD4  
+AD4 +-+ACM-define +AF8-Q+AF8-OWNER+AF8-CPU+AF8-OFFSET	1
+AD4 +-+ACM-define +AF8-Q+AF8-OWNER+AF8-CPU+AF8-BITS	14
+AD4 +-+ACM-define +AF8-Q+AF8-OWNER+AF8-CPU+AF8-MASK	+AF8-Q+AF8-SET+AF8-MASK(OWNER+AF8-CPU)
+AD4 +-
+AD4 +-+ACM-if CONFIG+AF8-NR+AF8-CPUS +AD4 (1U +ADwAPA +AF8-Q+AF8-OWNER+AF8-CPU+AF8-BITS)
+AD4 +-+ACM-error +ACI-qspinlock does not support such large CONFIG+AF8-NR+AF8-CPUS+ACI
+AD4 +-+ACM-endif
+AD4 +-
+AD4  +ACM-define +AF8-Q+AF8-MUST+AF8-Q+AF8-OFFSET	16
+AD4  +ACM-define +AF8-Q+AF8-MUST+AF8-Q+AF8-BITS		1
+AD4  +ACM-define +AF8-Q+AF8-MUST+AF8-Q+AF8-MASK		+AF8-Q+AF8-SET+AF8-MASK(MUST+AF8-Q)
+AD4 diff --git a/arch/powerpc/lib/qspinlock.c b/arch/powerpc/lib/qspinlock.c
+AD4 index a906cc8f15fa..aa26cfe21f18 100644
+AD4 --- a/arch/powerpc/lib/qspinlock.c
+AD4 +-+-+- b/arch/powerpc/lib/qspinlock.c
+AD4 +AEAAQA -50,7 +-50,7 +AEAAQA static inline int get+AF8-tail+AF8-cpu(u32 val)
+AD4  /+ACo Take the lock by setting the lock bit, no other CPUs will touch it. +ACo-/
+AD4  static +AF8AXw-always+AF8-inline void lock+AF8-set+AF8-locked(struct qspinlock +ACo-lock)
+AD4  +AHs
+AD4 -	u32 new +AD0 +AF8-Q+AF8-LOCKED+AF8-VAL+ADs
+AD4 +-	u32 new +AD0 queued+AF8-spin+AF8-get+AF8-locked+AF8-val()+ADs
+AD4  	u32 prev+ADs
+AD4  
+AD4  	asm volatile(
+AD4 +AEAAQA -68,7 +-68,7 +AEAAQA static +AF8AXw-always+AF8-inline void lock+AF8-set+AF8-locked(struct qspinlock +ACo-lock)
+AD4  /+ACo Take lock, clearing tail, cmpxchg with old (which must not be locked) +ACo-/
+AD4  static +AF8AXw-always+AF8-inline int trylock+AF8-clear+AF8-tail+AF8-cpu(struct qspinlock +ACo-lock, u32 old)
+AD4  +AHs
+AD4 -	u32 new +AD0 +AF8-Q+AF8-LOCKED+AF8-VAL+ADs
+AD4 +-	u32 new +AD0 queued+AF8-spin+AF8-get+AF8-locked+AF8-val()+ADs
+AD4  	u32 prev+ADs
+AD4  
+AD4  	BUG+AF8-ON(old +ACY +AF8-Q+AF8-LOCKED+AF8-VAL)+ADs
+AD4 +AEAAQA -116,7 +-116,7 +AEAAQA static +AF8AXw-always+AF8-inline u32 +AF8AXw-trylock+AF8-cmpxchg(struct qspinlock +ACo-lock, u32 old, u3
+AD4  /+ACo Take lock, preserving tail, cmpxchg with val (which must not be locked) +ACo-/
+AD4  static +AF8AXw-always+AF8-inline int trylock+AF8-with+AF8-tail+AF8-cpu(struct qspinlock +ACo-lock, u32 val)
+AD4  +AHs
+AD4 -	u32 newval +AD0 +AF8-Q+AF8-LOCKED+AF8-VAL +AHw (val +ACY +AF8-Q+AF8-TAIL+AF8-CPU+AF8-MASK)+ADs
+AD4 +-	u32 newval +AD0 queued+AF8-spin+AF8-get+AF8-locked+AF8-val() +AHw (val +ACY +AF8-Q+AF8-TAIL+AF8-CPU+AF8-MASK)+ADs
+AD4  
+AD4  	if (+AF8AXw-trylock+AF8-cmpxchg(lock, val, newval) +AD0APQ val)
+AD4  		return 1+ADs