From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22295C433EF for ; Thu, 2 Sep 2021 19:37:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8BC1860EE6 for ; Thu, 2 Sep 2021 19:37:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8BC1860EE6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:53654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLsWj-0000r0-Lg for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 15:37:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLsW8-00005V-SO for qemu-devel@nongnu.org; Thu, 02 Sep 2021 15:36:56 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58826 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLsW5-0007HI-QS for qemu-devel@nongnu.org; Thu, 02 Sep 2021 15:36:56 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=[192.168.50.176]) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1mLsVd-0004b3-Nt; Thu, 02 Sep 2021 20:36:29 +0100 To: Peter Maydell References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> <20210902102205.7554-5-mark.cave-ayland@ilande.co.uk> From: Mark Cave-Ayland Message-ID: <83018048-9501-9051-491c-f9165303da43@ilande.co.uk> Date: Thu, 2 Sep 2021 20:36:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: Re: [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-2.225, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 02/09/2021 20:31, Peter Maydell wrote: > On Thu, 2 Sept 2021 at 18:46, Mark Cave-Ayland > wrote: >> >> On 02/09/2021 16:42, Peter Maydell wrote: >> >>> On Thu, 2 Sept 2021 at 11:33, Mark Cave-Ayland >>> wrote: >>>> >>>> This new hardware reset function is to be called for both channels when the >>>> hardware reset bit is written to register WR9. Its initial implementation is >>>> the same as the existing escc_reset_chn() function used for device reset. >>>> >>>> Signed-off-by: Mark Cave-Ayland >>> >>> >>> The datasheet says the only differences between hard and soft >>> reset are for registers W9, W10, W11 and W14. I wasn't expecting >>> the functions to be completely separated out like this. >> >> I did consider doing it that way, but felt having the 2 separate functions was the >> easiest to read against the tables in the datasheet. What do you think would be the >> best way to organise the reset functions? > > I think having the hard-reset be "call the soft-reset and then > clear/set the handful of bits that hard-reset touches and > soft-reset doesn't" is probably clearer overall. Okay thanks, I'll give that a go (probably tomorrow now...) ATB, Mark.