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Wed, 8 Jul 2020 02:13:34 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3461BA4054; Wed, 8 Jul 2020 02:13:33 +0000 (GMT) Received: from [9.77.206.84] (unknown [9.77.206.84]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Wed, 8 Jul 2020 02:13:32 +0000 (GMT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs From: Athira Rajeev In-Reply-To: Date: Wed, 8 Jul 2020 07:43:30 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: <834C0090-CC20-4E20-8E9B-29362325B61A@linux.vnet.ibm.com> References: <1593595262-1433-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1593595262-1433-5-git-send-email-atrajeev@linux.vnet.ibm.com> To: Michael Neuling X-Mailer: Apple Mail (2.3608.80.23.2.2) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-07_15:2020-07-07, 2020-07-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 cotscore=-2147483648 clxscore=1015 phishscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007080007 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 07-Jul-2020, at 11:52 AM, Michael Neuling = wrote: >=20 > On Wed, 2020-07-01 at 05:20 -0400, Athira Rajeev wrote: >> From: Madhavan Srinivasan >>=20 >> Add power10 feature function to dt_cpu_ftrs.c along >> with a power10 specific init() to initialize pmu sprs. >=20 > Can you say why you're doing this? >=20 > Can you add some text about what you're doing to the BHRB in this = patch? Sure, I will include these information for commit message in the next = version Thanks Athira=20 >=20 > Mikey >=20 >>=20 >> Signed-off-by: Madhavan Srinivasan >> --- >> arch/powerpc/include/asm/reg.h | 3 +++ >> arch/powerpc/kernel/cpu_setup_power.S | 7 +++++++ >> arch/powerpc/kernel/dt_cpu_ftrs.c | 26 ++++++++++++++++++++++++++ >> 3 files changed, 36 insertions(+) >>=20 >> diff --git a/arch/powerpc/include/asm/reg.h = b/arch/powerpc/include/asm/reg.h >> index 21a1b2d..900ada1 100644 >> --- a/arch/powerpc/include/asm/reg.h >> +++ b/arch/powerpc/include/asm/reg.h >> @@ -1068,6 +1068,9 @@ >> #define MMCR0_PMC2_LOADMISSTIME 0x5 >> #endif >>=20 >> +/* BHRB disable bit for PowerISA v3.10 */ >> +#define MMCRA_BHRB_DISABLE 0x0000002000000000 >> + >> /* >> * SPRG usage: >> * >> diff --git a/arch/powerpc/kernel/cpu_setup_power.S >> b/arch/powerpc/kernel/cpu_setup_power.S >> index efdcfa7..e8b3370c 100644 >> --- a/arch/powerpc/kernel/cpu_setup_power.S >> +++ b/arch/powerpc/kernel/cpu_setup_power.S >> @@ -233,3 +233,10 @@ __init_PMU_ISA207: >> li r5,0 >> mtspr SPRN_MMCRS,r5 >> blr >> + >> +__init_PMU_ISA31: >> + li r5,0 >> + mtspr SPRN_MMCR3,r5 >> + LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE) >> + mtspr SPRN_MMCRA,r5 >> + blr >> diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c >> b/arch/powerpc/kernel/dt_cpu_ftrs.c >> index a0edeb3..14a513f 100644 >> --- a/arch/powerpc/kernel/dt_cpu_ftrs.c >> +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c >> @@ -449,6 +449,31 @@ static int __init feat_enable_pmu_power9(struct >> dt_cpu_feature *f) >> return 1; >> } >>=20 >> +static void init_pmu_power10(void) >> +{ >> + init_pmu_power9(); >> + >> + mtspr(SPRN_MMCR3, 0); >> + mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); >> +} >> + >> +static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f) >> +{ >> + hfscr_pmu_enable(); >> + >> + init_pmu_power10(); >> + init_pmu_registers =3D init_pmu_power10; >> + >> + cur_cpu_spec->cpu_features |=3D CPU_FTR_MMCRA; >> + cur_cpu_spec->cpu_user_features |=3D = PPC_FEATURE_PSERIES_PERFMON_COMPAT; >> + >> + cur_cpu_spec->num_pmcs =3D 6; >> + cur_cpu_spec->pmc_type =3D PPC_PMC_IBM; >> + cur_cpu_spec->oprofile_cpu_type =3D "ppc64/power10"; >> + >> + return 1; >> +} >> + >> static int __init feat_enable_tm(struct dt_cpu_feature *f) >> { >> #ifdef CONFIG_PPC_TRANSACTIONAL_MEM >> @@ -638,6 +663,7 @@ struct dt_cpu_feature_match { >> {"pc-relative-addressing", feat_enable, 0}, >> {"machine-check-power9", feat_enable_mce_power9, 0}, >> {"performance-monitor-power9", feat_enable_pmu_power9, 0}, >> + {"performance-monitor-power10", feat_enable_pmu_power10, 0}, >> {"event-based-branch-v3", feat_enable, 0}, >> {"random-number-generator", feat_enable, 0}, >> {"system-call-vectored", feat_disable, 0}, >=20