From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A99B3C433F5 for ; Wed, 23 Mar 2022 20:04:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232772AbiCWUFo (ORCPT ); Wed, 23 Mar 2022 16:05:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236041AbiCWUFm (ORCPT ); Wed, 23 Mar 2022 16:05:42 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAE048564F for ; Wed, 23 Mar 2022 13:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1648065850; x=1679601850; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=m/gVPbIOUw/B6IAh4NLNKzlzl2sk9Z1Cv3s7AOPuzdg=; b=znsB1SoME4ejUrVrsPivORYz1A+PXaF2s2UWj8fKV3yCaAmR7rCy6+78 sa6f6lDc1UVSAkKBsjaPfaNrcCJr0eMzDeUbJTWOCaKQMUfJm10gIV4hU G54HbbKYSCusxRzDjG92Yl6tGweg9owfZJD5zck6waI/nWdBYqd7gk2X1 I=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 23 Mar 2022 13:04:10 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2022 13:04:10 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 23 Mar 2022 13:04:09 -0700 Received: from [10.110.52.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 23 Mar 2022 13:04:09 -0700 Message-ID: <8372aeac-3d54-44f5-8341-0f9b1b604871@quicinc.com> Date: Wed, 23 Mar 2022 13:04:08 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH 11/22] drm/msm: Use drm_mode_init() for on-stack modes Content-Language: en-US To: Ville Syrjala , CC: , Rob Clark , "Sean Paul" , , References: <20220218100403.7028-1-ville.syrjala@linux.intel.com> <20220218100403.7028-12-ville.syrjala@linux.intel.com> From: Abhinav Kumar In-Reply-To: <20220218100403.7028-12-ville.syrjala@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2/18/2022 2:03 AM, Ville Syrjala wrote: > From: Ville Syrjälä > > Initialize on-stack modes with drm_mode_init() to guarantee > no stack garbage in the list head, or that we aren't copying > over another mode's list head. > > Based on the following cocci script, with manual fixups: > @decl@ > identifier M; > expression E; > @@ > - struct drm_display_mode M = E; > + struct drm_display_mode M; > > @@ > identifier decl.M; > expression decl.E; > statement S, S1; > @@ > struct drm_display_mode M; > ... when != S > + drm_mode_init(&M, &E); > + > S1 > > @@ > expression decl.E; > @@ > - &*E > + E > > Cc: Rob Clark > Cc: Sean Paul > Cc: Abhinav Kumar > Cc: linux-arm-msm@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Ville Syrjälä Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ddd9d89cd456..e7813c6f7bd9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -248,12 +248,13 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > unsigned long lock_flags; > struct dpu_hw_intf_cfg intf_cfg = { 0 }; > > + drm_mode_init(&mode, &phys_enc->cached_mode); > + > if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { > DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); > return; > } > > - mode = phys_enc->cached_mode; > if (!phys_enc->hw_intf->ops.setup_timing_gen) { > DPU_ERROR("timing engine setup is not supported\n"); > return; > @@ -652,7 +653,9 @@ static int dpu_encoder_phys_vid_get_frame_count( > { > struct intf_status s = {0}; > u32 fetch_start = 0; > - struct drm_display_mode mode = phys_enc->cached_mode; > + struct drm_display_mode mode; > + > + drm_mode_init(&mode, &phys_enc->cached_mode); > > if (!dpu_encoder_phys_vid_is_master(phys_enc)) > return -EINVAL; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 268A4C433EF for ; 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23 Mar 2022 13:04:10 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 23 Mar 2022 13:04:09 -0700 Received: from [10.110.52.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 23 Mar 2022 13:04:09 -0700 Message-ID: <8372aeac-3d54-44f5-8341-0f9b1b604871@quicinc.com> Date: Wed, 23 Mar 2022 13:04:08 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH 11/22] drm/msm: Use drm_mode_init() for on-stack modes Content-Language: en-US To: Ville Syrjala , References: <20220218100403.7028-1-ville.syrjala@linux.intel.com> <20220218100403.7028-12-ville.syrjala@linux.intel.com> From: Abhinav Kumar In-Reply-To: <20220218100403.7028-12-ville.syrjala@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, intel-gfx@lists.freedesktop.org, freedreno@lists.freedesktop.org, Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2/18/2022 2:03 AM, Ville Syrjala wrote: > From: Ville Syrjälä > > Initialize on-stack modes with drm_mode_init() to guarantee > no stack garbage in the list head, or that we aren't copying > over another mode's list head. > > Based on the following cocci script, with manual fixups: > @decl@ > identifier M; > expression E; > @@ > - struct drm_display_mode M = E; > + struct drm_display_mode M; > > @@ > identifier decl.M; > expression decl.E; > statement S, S1; > @@ > struct drm_display_mode M; > ... when != S > + drm_mode_init(&M, &E); > + > S1 > > @@ > expression decl.E; > @@ > - &*E > + E > > Cc: Rob Clark > Cc: Sean Paul > Cc: Abhinav Kumar > Cc: linux-arm-msm@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Ville Syrjälä Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ddd9d89cd456..e7813c6f7bd9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -248,12 +248,13 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > unsigned long lock_flags; > struct dpu_hw_intf_cfg intf_cfg = { 0 }; > > + drm_mode_init(&mode, &phys_enc->cached_mode); > + > if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { > DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); > return; > } > > - mode = phys_enc->cached_mode; > if (!phys_enc->hw_intf->ops.setup_timing_gen) { > DPU_ERROR("timing engine setup is not supported\n"); > return; > @@ -652,7 +653,9 @@ static int dpu_encoder_phys_vid_get_frame_count( > { > struct intf_status s = {0}; > u32 fetch_start = 0; > - struct drm_display_mode mode = phys_enc->cached_mode; > + struct drm_display_mode mode; > + > + drm_mode_init(&mode, &phys_enc->cached_mode); > > if (!dpu_encoder_phys_vid_is_master(phys_enc)) > return -EINVAL; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82EE7C433EF for ; Wed, 23 Mar 2022 20:04:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A818B10E092; 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Wed, 23 Mar 2022 13:04:09 -0700 Received: from [10.110.52.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 23 Mar 2022 13:04:09 -0700 Message-ID: <8372aeac-3d54-44f5-8341-0f9b1b604871@quicinc.com> Date: Wed, 23 Mar 2022 13:04:08 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Content-Language: en-US To: Ville Syrjala , References: <20220218100403.7028-1-ville.syrjala@linux.intel.com> <20220218100403.7028-12-ville.syrjala@linux.intel.com> From: Abhinav Kumar In-Reply-To: <20220218100403.7028-12-ville.syrjala@linux.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Subject: Re: [Intel-gfx] [PATCH 11/22] drm/msm: Use drm_mode_init() for on-stack modes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, intel-gfx@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 2/18/2022 2:03 AM, Ville Syrjala wrote: > From: Ville Syrjälä > > Initialize on-stack modes with drm_mode_init() to guarantee > no stack garbage in the list head, or that we aren't copying > over another mode's list head. > > Based on the following cocci script, with manual fixups: > @decl@ > identifier M; > expression E; > @@ > - struct drm_display_mode M = E; > + struct drm_display_mode M; > > @@ > identifier decl.M; > expression decl.E; > statement S, S1; > @@ > struct drm_display_mode M; > ... when != S > + drm_mode_init(&M, &E); > + > S1 > > @@ > expression decl.E; > @@ > - &*E > + E > > Cc: Rob Clark > Cc: Sean Paul > Cc: Abhinav Kumar > Cc: linux-arm-msm@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Ville Syrjälä Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index ddd9d89cd456..e7813c6f7bd9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -248,12 +248,13 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > unsigned long lock_flags; > struct dpu_hw_intf_cfg intf_cfg = { 0 }; > > + drm_mode_init(&mode, &phys_enc->cached_mode); > + > if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { > DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); > return; > } > > - mode = phys_enc->cached_mode; > if (!phys_enc->hw_intf->ops.setup_timing_gen) { > DPU_ERROR("timing engine setup is not supported\n"); > return; > @@ -652,7 +653,9 @@ static int dpu_encoder_phys_vid_get_frame_count( > { > struct intf_status s = {0}; > u32 fetch_start = 0; > - struct drm_display_mode mode = phys_enc->cached_mode; > + struct drm_display_mode mode; > + > + drm_mode_init(&mode, &phys_enc->cached_mode); > > if (!dpu_encoder_phys_vid_is_master(phys_enc)) > return -EINVAL;