From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Thierry, Michel" <michel.thierry@intel.com>
Subject: Re: [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode
Date: Wed, 17 Oct 2018 22:13:14 +0000 [thread overview]
Message-ID: <83F5C7385F545743AD4FB2A62F75B07347F78389@ORSMSX108.amr.corp.intel.com> (raw)
In-Reply-To: <20181004182939.7668-1-radhakrishna.sripada@intel.com>
>-----Original Message-----
>From: Sripada, Radhakrishna
>Sent: Thursday, October 4, 2018 11:30 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Chris Wilson
><chris@chris-wilson.co.uk>; Thierry, Michel <michel.thierry@intel.com>; Ausmus,
>James <james.ausmus@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode
>
>Gen11 Display suports 32 planes in total. Enable the new format in context status
>to be used and expanded to 32 planes.
>
>V2: Move the WA to display WA's(Chris)
>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Michel Thierry <michel.thierry@intel.com>
>Cc: James Ausmus <james.ausmus@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index a71c507cfb9b..4fb8e9eef312 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2573,6 +2573,7 @@ enum i915_power_well_id {
> /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ #define
>GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
>+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
>
> /* WaClearTdlStateAckDirtyBits */
> #define GEN8_STATE_ACK _MMIO(0x20F0)
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 1392aa56a55a..d4a464246760 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -8734,6 +8734,10 @@ static void icl_init_clock_gating(struct
>drm_i915_private *dev_priv)
> /* This is not an Wa. Enable to reduce Sampler power */
> I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) &
>~DFR_DISABLE);
>+
>+ /* WaEnable32PlaneMode:icl */
>+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
>+ _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> }
>
> static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>--
>2.9.3
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prev parent reply other threads:[~2018-10-17 22:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 18:29 [PATCH v2 1/6] drm/i915/icl: Add WaEnable32PlaneMode Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 2/6] drm/i915/icl: Implement Display WA_1405510057 Radhakrishna Sripada
2018-10-17 21:49 ` Srivatsa, Anusha
2018-10-04 18:29 ` [PATCH v2 3/6] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Radhakrishna Sripada
2018-10-12 19:01 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 4/6] drm/i915/icl: WaAllowUMDToModifySamplerMode Radhakrishna Sripada
2018-10-12 18:58 ` Radhakrishna Sripada
2018-10-04 18:29 ` [PATCH v2 5/6] drm/i915/icl: Add Wa_1406609255 Radhakrishna Sripada
2018-10-08 13:55 ` Mika Kuoppala
2018-10-09 7:18 ` Mika Kuoppala
2018-10-04 18:29 ` [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166 Radhakrishna Sripada
2018-10-08 14:02 ` Mika Kuoppala
2018-10-09 7:19 ` Mika Kuoppala
2018-10-04 19:08 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/6] drm/i915/icl: Add WaEnable32PlaneMode Patchwork
2018-10-05 2:32 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-17 22:13 ` Srivatsa, Anusha [this message]
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