[PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Anusha Srivatsa]

DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.

v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..aa8bfb754fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
-	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
-			    conn_state->max_requested_bpc);
+	/* Max DSC Input BPC for TGL+ is 12 */
+	if (INTEL_GEN(dev_priv) >= 12)
+		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+	else
+		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+				    conn_state->max_requested_bpc);
 
 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
 	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
-- 
2.21.0

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✗ Fi.CI.SPARSE: warning for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev2)

[Patchwork]

== Series Details ==

Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/63526/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dp/dsc: Add Support for all BPCs supported by TGL
-O:drivers/gpu/drm/i915/display/intel_dp.c:1917:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1919:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_dp.c:1921:31: warning: expression using sizeof(void)

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✗ Fi.CI.BAT: failure for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev2)

[Patchwork]

== Series Details ==

Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/63526/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6488 -> Patchwork_13663
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_13663 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13663, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13663:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
Known issues
------------

  Here are the changes found in Patchwork_13663 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [PASS][3] -> [FAIL][4] ([fdo#109483])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-apl-guc:         [PASS][5] -> [DMESG-WARN][6] ([fdo#108529] / [fdo#108566])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u3/igt@gem_ctx_exec@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-icl-u3/igt@gem_ctx_exec@basic.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][9] ([fdo#111108]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [FAIL][11] ([fdo#109635 ]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
    - fi-cml-u2:          [FAIL][13] ([fdo#110627]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [DMESG-WARN][15] ([fdo#106387]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108


Participating hosts (54 -> 47)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6488 -> Patchwork_13663

  CI_DRM_6488: bbf4d95db6732b16547dc9d849701ccf4189aa0d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5098: 41ff022b62b45a5b84504daa3537fa1b295b97c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13663: 7c8d95a6b3868325cf536693d28417b244281c23 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7c8d95a6b386 drm/dp/dsc: Add Support for all BPCs supported by TGL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13663/
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Manasi Navare]

On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating compression
> configuration.
> 
> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
> and use the value directly.(More such defines can be removed
> as part of future patches). (Ville)

IMO what Ville asked to do in his comment was to remove all the #defines
for the max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable
and that user does not have to hunt for the #defines for either of these.

> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0eb5d66f87a7..aa8bfb754fc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
>  
> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> -			    conn_state->max_requested_bpc);
> +	/* Max DSC Input BPC for TGL+ is 12 */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> +	else
> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> +				    conn_state->max_requested_bpc);

Use 10 here directly

>  
>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {

Use 8 here directly

Manasi
> -- 
> 2.21.0
> 
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Srivatsa, Anusha]

>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 16, 2019 11:15 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä <ville.syrjala@linux.intel.com>
>Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
>
>On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
>> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
>> engine in TGL supports 8, 10 and 12 BPC.
>> Add 12 BPC support for DSC while calculating compression
>> configuration.
>>
>> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
>> the value directly.(More such defines can be removed as part of future
>> patches). (Ville)
>
>IMO what Ville asked to do in his comment was to remove all the #defines for the
>max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
>that user does not have to hunt for the #defines for either of these.

Yes those changes can be part of a following patch. This is TGL specific.

Anusha 
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 0eb5d66f87a7..aa8bfb754fc1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
>intel_dp *intel_dp,
>>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>>  		return -EINVAL;
>>
>> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> -			    conn_state->max_requested_bpc);
>> +	/* Max DSC Input BPC for TGL+ is 12 */
>> +	if (INTEL_GEN(dev_priv) >= 12)
>> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
>> +	else
>> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> +				    conn_state->max_requested_bpc);
>
>Use 10 here directly
>
>>
>>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>
>Use 8 here directly
>
>Manasi
>> --
>> 2.21.0
>>
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Manasi Navare]

On Tue, Jul 16, 2019 at 01:26:19PM -0700, Srivatsa, Anusha wrote:
> 
> 
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Tuesday, July 16, 2019 11:15 AM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Subject: Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
> >
> >On Mon, Jul 15, 2019 at 04:40:56PM -0700, Anusha Srivatsa wrote:
> >> DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC
> >> engine in TGL supports 8, 10 and 12 BPC.
> >> Add 12 BPC support for DSC while calculating compression
> >> configuration.
> >>
> >> v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use
> >> the value directly.(More such defines can be removed as part of future
> >> patches). (Ville)
> >
> >IMO what Ville asked to do in his comment was to remove all the #defines for the
> >max DSC BPC so remove the ones for 8 and 10 also to mak eit more readable and
> >that user does not have to hunt for the #defines for either of these.
> 
> Yes those changes can be part of a following patch. This is TGL specific.

IMO, you could just make them in the same patch since they are minor changes
happening because of diferent max limits for TGL, so just say in the commit message
while at it also remove the #defines and use the values directly for ICL limits as well.

Manasi

> 
> Anusha 
> >>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++--
> >>  1 file changed, 6 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> b/drivers/gpu/drm/i915/display/intel_dp.c
> >> index 0eb5d66f87a7..aa8bfb754fc1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> @@ -1914,8 +1914,12 @@ static int intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> >>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >>  		return -EINVAL;
> >>
> >> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> -			    conn_state->max_requested_bpc);
> >> +	/* Max DSC Input BPC for TGL+ is 12 */
> >> +	if (INTEL_GEN(dev_priv) >= 12)
> >> +		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
> >> +	else
> >> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> +				    conn_state->max_requested_bpc);
> >
> >Use 10 here directly
> >
> >>
> >>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> >
> >Use 8 here directly
> >
> >Manasi
> >> --
> >> 2.21.0
> >>
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[PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Anusha Srivatsa]

DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.

v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)

v3: Use values directly instead of accessing the defines
everytime for min and max DSC BPC.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..947c7e911304 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -69,8 +69,6 @@
 
 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
-#define DP_DSC_MIN_SUPPORTED_BPC		8
-#define DP_DSC_MAX_SUPPORTED_BPC		10
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -1914,11 +1912,17 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
-	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
-			    conn_state->max_requested_bpc);
+	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+	if (INTEL_GEN(dev_priv) >= 12)
+		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+	else
+		dsc_max_bpc = min_t(u8, 10,
+				    conn_state->max_requested_bpc);
 
 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
-	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
+
+	/* Min Input BPC for ICL+ is 8 */
+	if (pipe_bpp < 8 * 3) {
 		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
 		return -EINVAL;
 	}
-- 
2.21.0

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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Srivatsa, Anusha]

>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, July 12, 2019 10:34 AM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: Navare, Manasi D <manasi.d.navare@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported
>by TGL
>
>On Fri, Jul 12, 2019 at 05:29:16PM +0000, Srivatsa, Anusha wrote:
>>
>>
>> >-----Original Message-----
>> >From: Navare, Manasi D
>> >Sent: Thursday, July 11, 2019 10:24 AM
>> >To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>> >gfx@lists.freedesktop.org
>> >Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs
>> >supported by TGL
>> >
>> >On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
>> >> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
>> >> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC.
>> >> > But DSC engine in TGL supports 8, 10 and 12 BPC.
>> >> > Add 12 BPC support for DSC while calculating compression
>> >> > configuration.
>> >> >
>> >> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
>> >> >  1 file changed, 7 insertions(+), 2 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > index 0bdb7ecc5a81..cd089643c80d 100644
>> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> >> > @@ -71,6 +71,7 @@
>> >> >  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
>> >> >  #define DP_DSC_MIN_SUPPORTED_BPC		8
>> >> >  #define DP_DSC_MAX_SUPPORTED_BPC		10
>> >> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12
>> >>
>> >> These defines aren't doing any good IMO. I'd just nuke them.
>> >
>> >So just remove all the #defines and use the values directly?
>>
>> Wont it make it less readable?
>
>It will be more readable because you don't have to go looking for those defines.
Ok. Then remove all #defines like Manasi pointed out?

Anusha 
>>
>> >>
>> >> >
>> >> >  /* DP DSC throughput values used for slice count calculations KPixels/s */
>> >> >  #define DP_DSC_PEAK_PIXEL_RATE			2720000
>> >> > @@ -1911,8 +1912,12 @@ static int
>> >> > intel_dp_dsc_compute_config(struct
>> >intel_dp *intel_dp,
>> >> >  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> >> >  		return -EINVAL;
>> >> >
>> >> > -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> >> > -			    conn_state->max_requested_bpc);
>> >> > +	if (INTEL_GEN(dev_priv) > 11)
>> >>
>> >> More customarily >= 12
>> >
>> >I agree
>>
>> Makes sense.
>>
>> Anusha
>> >Manasi
>> >
>> >>
>> >> > +		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
>> >> > +				    conn_state->max_requested_bpc);
>> >> > +	else
>> >> > +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> >> > +				    conn_state->max_requested_bpc);
>> >> >
>> >> >  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>> >> >  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>> >> > --
>> >> > 2.21.0
>> >> >
>> >> > _______________________________________________
>> >> > Intel-gfx mailing list
>> >> > Intel-gfx@lists.freedesktop.org
>> >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>
>> >> --
>> >> Ville Syrjälä
>> >> Intel
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Ville Syrjälä]

On Fri, Jul 12, 2019 at 05:29:16PM +0000, Srivatsa, Anusha wrote:
> 
> 
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Thursday, July 11, 2019 10:24 AM
> >To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> >gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported
> >by TGL
> >
> >On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> >> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> >> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But
> >> > DSC engine in TGL supports 8, 10 and 12 BPC.
> >> > Add 12 BPC support for DSC while calculating compression
> >> > configuration.
> >> >
> >> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
> >> >  1 file changed, 7 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > index 0bdb7ecc5a81..cd089643c80d 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >> > @@ -71,6 +71,7 @@
> >> >  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
> >> >  #define DP_DSC_MIN_SUPPORTED_BPC		8
> >> >  #define DP_DSC_MAX_SUPPORTED_BPC		10
> >> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12
> >>
> >> These defines aren't doing any good IMO. I'd just nuke them.
> >
> >So just remove all the #defines and use the values directly?
> 
> Wont it make it less readable?

It will be more readable because you don't have to go looking for those
defines.

> 
> >>
> >> >
> >> >  /* DP DSC throughput values used for slice count calculations KPixels/s */
> >> >  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> >> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> >> >  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >> >  		return -EINVAL;
> >> >
> >> > -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> > -			    conn_state->max_requested_bpc);
> >> > +	if (INTEL_GEN(dev_priv) > 11)
> >>
> >> More customarily >= 12
> >
> >I agree
> 
> Makes sense.
> 
> Anusha 
> >Manasi
> >
> >>
> >> > +		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> >> > +				    conn_state->max_requested_bpc);
> >> > +	else
> >> > +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> >> > +				    conn_state->max_requested_bpc);
> >> >
> >> >  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >> >  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> >> > --
> >> > 2.21.0
> >> >
> >> > _______________________________________________
> >> > Intel-gfx mailing list
> >> > Intel-gfx@lists.freedesktop.org
> >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >> --
> >> Ville Syrjälä
> >> Intel
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Srivatsa, Anusha]

>-----Original Message-----
>From: Navare, Manasi D
>Sent: Thursday, July 11, 2019 10:24 AM
>To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported
>by TGL
>
>On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
>> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
>> > DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But
>> > DSC engine in TGL supports 8, 10 and 12 BPC.
>> > Add 12 BPC support for DSC while calculating compression
>> > configuration.
>> >
>> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
>> >  1 file changed, 7 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 0bdb7ecc5a81..cd089643c80d 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -71,6 +71,7 @@
>> >  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
>> >  #define DP_DSC_MIN_SUPPORTED_BPC		8
>> >  #define DP_DSC_MAX_SUPPORTED_BPC		10
>> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12
>>
>> These defines aren't doing any good IMO. I'd just nuke them.
>
>So just remove all the #defines and use the values directly?

Wont it make it less readable?

>>
>> >
>> >  /* DP DSC throughput values used for slice count calculations KPixels/s */
>> >  #define DP_DSC_PEAK_PIXEL_RATE			2720000
>> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct
>intel_dp *intel_dp,
>> >  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>> >  		return -EINVAL;
>> >
>> > -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> > -			    conn_state->max_requested_bpc);
>> > +	if (INTEL_GEN(dev_priv) > 11)
>>
>> More customarily >= 12
>
>I agree

Makes sense.

Anusha 
>Manasi
>
>>
>> > +		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
>> > +				    conn_state->max_requested_bpc);
>> > +	else
>> > +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
>> > +				    conn_state->max_requested_bpc);
>> >
>> >  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>> >  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
>> > --
>> > 2.21.0
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Ville Syrjälä
>> Intel
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Manasi Navare]

On Thu, Jul 11, 2019 at 04:47:17PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> > DSC engine on ICL supports only 8 and 10 BPC as the input
> > BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> > Add 12 BPC support for DSC while calculating compression
> > configuration.
> > 
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0bdb7ecc5a81..cd089643c80d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -71,6 +71,7 @@
> >  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
> >  #define DP_DSC_MIN_SUPPORTED_BPC		8
> >  #define DP_DSC_MAX_SUPPORTED_BPC		10
> > +#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12
> 
> These defines aren't doing any good IMO. I'd just nuke them.

So just remove all the #defines and use the values directly?

> 
> >  
> >  /* DP DSC throughput values used for slice count calculations KPixels/s */
> >  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> > @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> >  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> >  		return -EINVAL;
> >  
> > -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > -			    conn_state->max_requested_bpc);
> > +	if (INTEL_GEN(dev_priv) > 11)
> 
> More customarily >= 12

I agree

Manasi

> 
> > +		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> > +				    conn_state->max_requested_bpc);
> > +	else
> > +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> > +				    conn_state->max_requested_bpc);
> >  
> >  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
> >  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> > -- 
> > 2.21.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Ville Syrjälä]

On Wed, Jul 10, 2019 at 04:09:21PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating compression
> configuration.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0bdb7ecc5a81..cd089643c80d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -71,6 +71,7 @@
>  #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
>  #define DP_DSC_MIN_SUPPORTED_BPC		8
>  #define DP_DSC_MAX_SUPPORTED_BPC		10
> +#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12

These defines aren't doing any good IMO. I'd just nuke them.

>  
>  /* DP DSC throughput values used for slice count calculations KPixels/s */
>  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> @@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
>  
> -	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> -			    conn_state->max_requested_bpc);
> +	if (INTEL_GEN(dev_priv) > 11)

More customarily >= 12

> +		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
> +				    conn_state->max_requested_bpc);
> +	else
> +		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
> +				    conn_state->max_requested_bpc);
>  
>  	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
>  	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL

[Anusha Srivatsa]

DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0bdb7ecc5a81..cd089643c80d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -71,6 +71,7 @@
 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
 #define DP_DSC_MIN_SUPPORTED_BPC		8
 #define DP_DSC_MAX_SUPPORTED_BPC		10
+#define TGL_DP_DSC_MAX_SUPPORTED_BPC		12
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -1911,8 +1912,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
-	dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
-			    conn_state->max_requested_bpc);
+	if (INTEL_GEN(dev_priv) > 11)
+		dsc_max_bpc = min_t(u8, TGL_DP_DSC_MAX_SUPPORTED_BPC,
+				    conn_state->max_requested_bpc);
+	else
+		dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
+				    conn_state->max_requested_bpc);
 
 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
 	if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
-- 
2.21.0

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