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From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Jinyang He" <hejinyang@loongson.cn>,
	"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
	"Steven Rostedt" <rostedt@goodmis.org>,
	"Ingo Molnar" <mingo@redhat.com>
Cc: "Wu Zhangjin" <wuzhangjin@gmail.com>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
	linux-kernel@vger.kernel.org,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Tiezhu Yang" <yangtiezhu@loongson.cn>
Subject: Re: [PATCH 1/3] MIPS: ftrace: Fix N32 save registers
Date: Mon, 01 Feb 2021 12:03:02 +0800	[thread overview]
Message-ID: <83e49b6e-9c9d-407e-8ac1-f3fad63df915@www.fastmail.com> (raw)
In-Reply-To: <d9548ffc-9d91-baf6-107a-af1b174db29b@loongson.cn>



On Mon, Feb 1, 2021, at 9:12 AM, Jinyang He wrote:
> On 01/31/2021 06:38 PM, Jiaxun Yang wrote:
> 
> >
> > On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote:
> >> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7.
> > Do we have NEW kernel build?
> > CONFIG_64BIT assumed N64 as kernel ABI.
> >
> >
> > -Jiaxun
> Hi, Jiaxun,
> 
> Thank you for your reply, and now I know. Before that, I saw the macro
> from arch/mips/include/asm/regdef.h and thought it needed to be modified
> here. But that seems have no sence.
> Please ignore this patch.

I guess that's for uapi consideration.

Thanks.


- Jiaxun



> 
> Thanks,
> Jinyang
> 
> >> Signed-off-by: Jinyang He <hejinyang@loongson.cn>
> >> ---
> >>   arch/mips/kernel/mcount.S | 4 ++--
> >>   1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
> >> index cff52b2..808257a 100644
> >> --- a/arch/mips/kernel/mcount.S
> >> +++ b/arch/mips/kernel/mcount.S
> >> @@ -27,7 +27,7 @@
> >>   	PTR_S	a1, PT_R5(sp)
> >>   	PTR_S	a2, PT_R6(sp)
> >>   	PTR_S	a3, PT_R7(sp)
> >> -#ifdef CONFIG_64BIT
> >> +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
> >>   	PTR_S	a4, PT_R8(sp)
> >>   	PTR_S	a5, PT_R9(sp)
> >>   	PTR_S	a6, PT_R10(sp)
> >> @@ -42,7 +42,7 @@
> >>   	PTR_L	a1, PT_R5(sp)
> >>   	PTR_L	a2, PT_R6(sp)
> >>   	PTR_L	a3, PT_R7(sp)
> >> -#ifdef CONFIG_64BIT
> >> +#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
> >>   	PTR_L	a4, PT_R8(sp)
> >>   	PTR_L	a5, PT_R9(sp)
> >>   	PTR_L	a6, PT_R10(sp)
> >> -- 
> >> 2.1.0
> >>
> >>
> 
>

-- 
- Jiaxun

  reply	other threads:[~2021-02-01  4:04 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-31  8:14 [PATCH 1/3] MIPS: ftrace: Fix N32 save registers Jinyang He
2021-01-31  8:14 ` [PATCH 2/3] MIPS: ftrace: Combine ftrace_modify_code* into one function Jinyang He
2021-01-31  8:14 ` [PATCH 3/3] MIPS: ftrace: Add DYNAMIC_FTRACE_WITH_REGS support Jinyang He
2021-02-01 14:56   ` Steven Rostedt
2021-02-02 12:21     ` Jinyang He
     [not found] ` <b1a5eae4-2032-4ace-aa48-a21893e47528@www.fastmail.com>
2021-02-01  1:12   ` [PATCH 1/3] MIPS: ftrace: Fix N32 save registers Jinyang He
2021-02-01  4:03     ` Jiaxun Yang [this message]
2021-02-13 15:17       ` Maciej W. Rozycki

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