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Sun, 10 Dec 2023 06:38:41 -0800 (PST) Received: from [192.168.1.20] ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm12119612wmb.27.2023.12.10.06.38.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Dec 2023 06:38:41 -0800 (PST) Message-ID: <8400d76b-2a04-4d60-ad6c-954dca07562f@linaro.org> Date: Sun, 10 Dec 2023 15:38:38 +0100 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 18/20] arm64: dts: exynos: google: Add initial Google gs101 SoC support Content-Language: en-US To: Peter Griffin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org References: <20231209233106.147416-1-peter.griffin@linaro.org> <20231209233106.147416-19-peter.griffin@linaro.org> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/12/2023 00:31, Peter Griffin wrote: > Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 > (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. > > It features: > * 4xA55 Little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > ... > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..68b7bc47c91b > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright 2020-2023 Google LLC > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ Header guards don't really match location. > + > +#define GS101_PIN_PULL_NONE 0 > +#define GS101_PIN_PULL_DOWN 1 > +#define GS101_PIN_PULL_UP 3 > + > +/* Pin function in power down mode */ > +#define GS101_PIN_PDN_OUT0 0 > +#define GS101_PIN_PDN_OUT1 1 > +#define GS101_PIN_PDN_INPUT 2 > +#define GS101_PIN_PDN_PREV 3 > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#define GS101_PIN_FUNC_INPUT 0 > +#define GS101_PIN_FUNC_OUTPUT 1 > +#define GS101_PIN_FUNC_2 2 > +#define GS101_PIN_FUNC_3 3 > +#define GS101_PIN_FUNC_EINT 0xf > + > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > new file mode 100644 > index 000000000000..60e112d25246 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -0,0 +1,476 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "google,gs101"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_gpio_alive; > + pinctrl1 = &pinctrl_far_alive; > + pinctrl2 = &pinctrl_gsacore; > + pinctrl3 = &pinctrl_gsactrl; > + pinctrl4 = &pinctrl_peric0; > + pinctrl5 = &pinctrl_peric1; > + pinctrl6 = &pinctrl_hsi1; > + pinctrl7 = &pinctrl_hsi2; > + }; > + > + pmu-0 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = ; > + }; > + > + pmu-1 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = ; > + }; > + > + pmu-2 { > + compatible = "arm,cortex-x1-pmu"; > + interrupts = ; > + }; > + > + pmu-3 { > + compatible = "arm,dsu-pmu"; > + interrupts = ; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; Keep alphabetical order of top-level nodes. pmu should be before psci > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { clock-3 > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; > + clock-output-names = "pclk"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; ... > + > + /* ect node is required to be present by bootloader */ > + ect { > + }; alphabetical order > + > + ext_24_5m: clock-1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: clock-2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext-200m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + tpu_fw_reserved: tpu-fw@93000000 { > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss-log-reserved@fd3f0000 { > + reg = <0x0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > + reg = <0x0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr-log-reserved@fd800000 { > + reg = <0x0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > + reg = <0x0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + timer { alphabetical order, so this goes to the end > + compatible = "arm,armv8-timer"; > + interrupts = > + , > + , > + , > + ; > + clock-frequency = <24576000>; I don't remember if you already got Marc's wrath, so just in case: are you sure it is needed? Anyway, this is board specific, not SoC. > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x10010000 0x8000>; > + #clock-cells = <1>; > + clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, One space after = > + <&cmu_top CLK_DOUT_CMU_MISC_SSS>; > + clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10060000 0x100>; > + interrupts = ; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, Join lines (clocks = ). Same in other places. > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + status = "disabled"; > + }; > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10070000 0x100>; > + interrupts = ; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@10400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-controller; > + reg = <0x10400000 0x10000>, /* GICD */ > + <0x10440000 0x100000>;/* GICR * 8 */ > + interrupts = ; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5>; > + }; > + > + ppi_cluster2: interrupt-partition-2 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + }; > + > + sysreg_peric0: syscon@10820000 { > + compatible = "google,gs101-peric0-sysreg", "syscon"; > + reg = <0x10820000 0x10000>; > + }; > + > + pinctrl_peric0: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10840000 0x00001000>; > + interrupts = ; > + }; > + > + usi_uart: usi@10a000c0 { > + compatible = "google,gs101-usi", > + "samsung,exynos850-usi"; > + reg = <0x10a000c0 0x20>; > + samsung,sysreg = <&sysreg_peric0 0x1020>; > + samsung,mode = ; vendor properties go to the end, after standard properties, before status. https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst?h=dt/next&id=0d3a771610d0e155c9aa305f142f84dda5030fae#n122 > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clocks = <&dummy_clk>, <&dummy_clk>; > + clock-names = "pclk", "ipclk"; > + status = "disabled"; > + > + serial_0: serial@10a00000 { > + compatible = "google,gs101-uart"; > + reg = <0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; Ditto > + interrupts = + IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clock-names = "uart", "clk_uart_baud0"; > + status = "disabled"; > + }; > + }; Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CF94C4167B for ; Sun, 10 Dec 2023 14:39:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/12/2023 00:31, Peter Griffin wrote: > Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 > (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile > phones. > > It features: > * 4xA55 Little cluster > * 2xA76 Mid cluster > * 2xX1 Big cluster > ... > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > new file mode 100644 > index 000000000000..68b7bc47c91b > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Pinctrl binding constants for GS101 > + * > + * Copyright 2020-2023 Google LLC > + */ > + > +#ifndef __DT_BINDINGS_PINCTRL_GS101_H__ > +#define __DT_BINDINGS_PINCTRL_GS101_H__ Header guards don't really match location. > + > +#define GS101_PIN_PULL_NONE 0 > +#define GS101_PIN_PULL_DOWN 1 > +#define GS101_PIN_PULL_UP 3 > + > +/* Pin function in power down mode */ > +#define GS101_PIN_PDN_OUT0 0 > +#define GS101_PIN_PDN_OUT1 1 > +#define GS101_PIN_PDN_INPUT 2 > +#define GS101_PIN_PDN_PREV 3 > + > +/* GS101 drive strengths */ > +#define GS101_PIN_DRV_2_5_MA 0 > +#define GS101_PIN_DRV_5_MA 1 > +#define GS101_PIN_DRV_7_5_MA 2 > +#define GS101_PIN_DRV_10_MA 3 > + > +#define GS101_PIN_FUNC_INPUT 0 > +#define GS101_PIN_FUNC_OUTPUT 1 > +#define GS101_PIN_FUNC_2 2 > +#define GS101_PIN_FUNC_3 3 > +#define GS101_PIN_FUNC_EINT 0xf > + > +#endif /* __DT_BINDINGS_PINCTRL_GS101_H__ */ > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > new file mode 100644 > index 000000000000..60e112d25246 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -0,0 +1,476 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * GS101 SoC > + * > + * Copyright 2019-2023 Google LLC > + * Copyright 2023 Linaro Ltd - > + */ > + > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "google,gs101"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_gpio_alive; > + pinctrl1 = &pinctrl_far_alive; > + pinctrl2 = &pinctrl_gsacore; > + pinctrl3 = &pinctrl_gsactrl; > + pinctrl4 = &pinctrl_peric0; > + pinctrl5 = &pinctrl_peric1; > + pinctrl6 = &pinctrl_hsi1; > + pinctrl7 = &pinctrl_hsi2; > + }; > + > + pmu-0 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = ; > + }; > + > + pmu-1 { > + compatible = "arm,cortex-a76-pmu"; > + interrupts = ; > + }; > + > + pmu-2 { > + compatible = "arm,cortex-x1-pmu"; > + interrupts = ; > + }; > + > + pmu-3 { > + compatible = "arm,dsu-pmu"; > + interrupts = ; > + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, > + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; > + }; Keep alphabetical order of top-level nodes. pmu should be before psci > + > + /* TODO replace with CCF clock */ > + dummy_clk: oscillator { clock-3 > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12345>; > + clock-output-names = "pclk"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu6>; > + }; > + core1 { > + cpu = <&cpu7>; > + }; > + }; > + }; ... > + > + /* ect node is required to be present by bootloader */ > + ect { > + }; alphabetical order > + > + ext_24_5m: clock-1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "oscclk"; > + }; > + > + ext_200m: clock-2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "ext-200m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + > + gsa_reserved_protected: gsa@90200000 { > + reg = <0x0 0x90200000 0x400000>; > + no-map; > + }; > + > + tpu_fw_reserved: tpu-fw@93000000 { > + reg = <0x0 0x93000000 0x1000000>; > + no-map; > + }; > + > + aoc_reserve: aoc@94000000 { > + reg = <0x0 0x94000000 0x03000000>; > + no-map; > + }; > + > + abl_reserved: abl@f8800000 { > + reg = <0x0 0xf8800000 0x02000000>; > + no-map; > + }; > + > + dss_log_reserved: dss-log-reserved@fd3f0000 { > + reg = <0x0 0xfd3f0000 0x0000e000>; > + no-map; > + }; > + > + debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { > + reg = <0x0 0xfd3fe000 0x00001000>; > + no-map; > + }; > + > + bldr_log_reserved: bldr-log-reserved@fd800000 { > + reg = <0x0 0xfd800000 0x00100000>; > + no-map; > + }; > + > + bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { > + reg = <0x0 0xfd900000 0x00002000>; > + no-map; > + }; > + }; > + > + timer { alphabetical order, so this goes to the end > + compatible = "arm,armv8-timer"; > + interrupts = > + , > + , > + , > + ; > + clock-frequency = <24576000>; I don't remember if you already got Marc's wrath, so just in case: are you sure it is needed? Anyway, this is board specific, not SoC. > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x40000000>; > + > + cmu_misc: clock-controller@10010000 { > + compatible = "google,gs101-cmu-misc"; > + reg = <0x10010000 0x8000>; > + #clock-cells = <1>; > + clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, One space after = > + <&cmu_top CLK_DOUT_CMU_MISC_SSS>; > + clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; > + }; > + > + watchdog_cl0: watchdog@10060000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10060000 0x100>; > + interrupts = ; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, Join lines (clocks = ). Same in other places. > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <0>; > + status = "disabled"; > + }; > + > + watchdog_cl1: watchdog@10070000 { > + compatible = "google,gs101-wdt"; > + reg = <0x10070000 0x100>; > + interrupts = ; > + clocks = > + <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, > + <&ext_24_5m>; > + clock-names = "watchdog", "watchdog_src"; > + samsung,syscon-phandle = <&pmu_system_controller>; > + samsung,cluster-index = <1>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@10400000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-controller; > + reg = <0x10400000 0x10000>, /* GICD */ > + <0x10440000 0x100000>;/* GICR * 8 */ > + interrupts = ; > + > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5>; > + }; > + > + ppi_cluster2: interrupt-partition-2 { > + affinity = <&cpu6 &cpu7>; > + }; > + }; > + }; > + > + sysreg_peric0: syscon@10820000 { > + compatible = "google,gs101-peric0-sysreg", "syscon"; > + reg = <0x10820000 0x10000>; > + }; > + > + pinctrl_peric0: pinctrl@10840000 { > + compatible = "google,gs101-pinctrl"; > + reg = <0x10840000 0x00001000>; > + interrupts = ; > + }; > + > + usi_uart: usi@10a000c0 { > + compatible = "google,gs101-usi", > + "samsung,exynos850-usi"; > + reg = <0x10a000c0 0x20>; > + samsung,sysreg = <&sysreg_peric0 0x1020>; > + samsung,mode = ; vendor properties go to the end, after standard properties, before status. https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst?h=dt/next&id=0d3a771610d0e155c9aa305f142f84dda5030fae#n122 > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clocks = <&dummy_clk>, <&dummy_clk>; > + clock-names = "pclk", "ipclk"; > + status = "disabled"; > + > + serial_0: serial@10a00000 { > + compatible = "google,gs101-uart"; > + reg = <0x10a00000 0xc0>; > + reg-io-width = <4>; > + samsung,uart-fifosize = <256>; Ditto > + interrupts = + IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&dummy_clk 0>, <&dummy_clk 0>; > + clock-names = "uart", "clk_uart_baud0"; > + status = "disabled"; > + }; > + }; Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel