Re: [PATCH v4 11/11] arm: dts: qcom: mdm9615: remove useless amba subnode

[Konrad Dybcio <konrad.dybcio@somainline.org>]

On 21.10.2022 11:06, Neil Armstrong wrote:
> The separate amba device node doesn't add anything significant to the
> DT. The OF parsing code already creates amba_device or platform_device
> depending on the compatibility lists.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
If we ever wanted to do split buses, per-NoC nodes would make sense, but
as you mentioned, this does not, really.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>

Konrad
>  arch/arm/boot/dts/qcom-mdm9615.dtsi | 78 +++++++++++++++++--------------------
>  1 file changed, 36 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> index 9d950f96280d..482fd246321c 100644
> --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
> +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
> @@ -314,49 +314,43 @@ sdcc2bam: dma-controller@12142000{
>  			qcom,ee = <0>;
>  		};
>  
> -		amba {
> -			compatible = "simple-bus";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges;
> -			sdcc1: mmc@12180000 {
> -				status = "disabled";
> -				compatible = "arm,pl18x", "arm,primecell";
> -				arm,primecell-periphid = <0x00051180>;
> -				reg = <0x12180000 0x2000>;
> -				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
> -				clock-names = "mclk", "apb_pclk";
> -				bus-width = <8>;
> -				max-frequency = <48000000>;
> -				cap-sd-highspeed;
> -				cap-mmc-highspeed;
> -				vmmc-supply = <&vsdcc_fixed>;
> -				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
> -				dma-names = "tx", "rx";
> -				assigned-clocks = <&gcc SDC1_CLK>;
> -				assigned-clock-rates = <400000>;
> -			};
> +		sdcc1: mmc@12180000 {
> +			status = "disabled";
> +			compatible = "arm,pl18x", "arm,primecell";
> +			arm,primecell-periphid = <0x00051180>;
> +			reg = <0x12180000 0x2000>;
> +			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
> +			clock-names = "mclk", "apb_pclk";
> +			bus-width = <8>;
> +			max-frequency = <48000000>;
> +			cap-sd-highspeed;
> +			cap-mmc-highspeed;
> +			vmmc-supply = <&vsdcc_fixed>;
> +			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
> +			dma-names = "tx", "rx";
> +			assigned-clocks = <&gcc SDC1_CLK>;
> +			assigned-clock-rates = <400000>;
> +		};
>  
> -			sdcc2: mmc@12140000 {
> -				compatible = "arm,pl18x", "arm,primecell";
> -				arm,primecell-periphid = <0x00051180>;
> -				status = "disabled";
> -				reg = <0x12140000 0x2000>;
> -				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> -				clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
> -				clock-names = "mclk", "apb_pclk";
> -				bus-width = <4>;
> -				cap-sd-highspeed;
> -				cap-mmc-highspeed;
> -				max-frequency = <48000000>;
> -				no-1-8-v;
> -				vmmc-supply = <&vsdcc_fixed>;
> -				dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
> -				dma-names = "tx", "rx";
> -				assigned-clocks = <&gcc SDC2_CLK>;
> -				assigned-clock-rates = <400000>;
> -			};
> +		sdcc2: mmc@12140000 {
> +			compatible = "arm,pl18x", "arm,primecell";
> +			arm,primecell-periphid = <0x00051180>;
> +			status = "disabled";
> +			reg = <0x12140000 0x2000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
> +			clock-names = "mclk", "apb_pclk";
> +			bus-width = <4>;
> +			cap-sd-highspeed;
> +			cap-mmc-highspeed;
> +			max-frequency = <48000000>;
> +			no-1-8-v;
> +			vmmc-supply = <&vsdcc_fixed>;
> +			dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
> +			dma-names = "tx", "rx";
> +			assigned-clocks = <&gcc SDC2_CLK>;
> +			assigned-clock-rates = <400000>;
>  		};
>  
>  		tcsr: syscon@1a400000 {
>