From: Andrew Cooper <andrew.cooper3@citrix.com>
To: "Roger Pau Monné" <roger.pau@citrix.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
Julien Grall <julien@xen.org>, Wei Liu <wl@xen.org>,
Ian Jackson <ian.jackson@eu.citrix.com>,
George Dunlap <george.dunlap@citrix.com>,
Jan Beulich <jbeulich@suse.com>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel
Date: Thu, 21 May 2020 17:27:29 +0100 [thread overview]
Message-ID: <84486d84-4452-af18-f7e7-753faf5a125d@citrix.com> (raw)
In-Reply-To: <20200521084523.GP54375@Air-de-Roger>
On 21/05/2020 09:45, Roger Pau Monné wrote:
> On Wed, May 20, 2020 at 10:30:11PM +0100, Andrew Cooper wrote:
>> On 15/05/2020 14:58, Roger Pau Monne wrote:
>>> Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125,
>>> BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be
>>> Dispatched Before an Interrupt of The Same Priority Completes".
>> HSM175 et al, so presumably a HSD, and HSE as well.
>>
>> On the broadwell side at least, BDD BDW in addition
> But those are a different errata AFAICT ('An APIC Timer Interrupt
> During Core C6 Entry May be Lost') and the workaround should also be
> different I think.
Hmm, so it is.
The issue in question here definitely does affect Haswell, because that
is where we first observed it. There was also a report on xen-devel
against Haswell.
If the errata are missing, then I think Intel needs some more chasing to
work out the real extent of the problems.
> We should mark the lapic timer as not reliable on
> C6 or higher states in lapic_timer_reliable_states, so that it's
> disabled before entering sleep?
Probably should.
~Andrew
prev parent reply other threads:[~2020-05-21 16:27 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 13:58 [PATCH v3 0/2] x86/idle: fix for Intel ISR errata Roger Pau Monne
2020-05-15 13:58 ` [PATCH v3 1/2] x86/idle: rework C6 EOI workaround Roger Pau Monne
2020-05-18 14:48 ` Jan Beulich
2020-05-15 13:58 ` [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel Roger Pau Monne
2020-05-18 15:05 ` Jan Beulich
2020-05-18 15:45 ` Roger Pau Monné
2020-05-18 15:47 ` Jan Beulich
2020-05-20 18:38 ` Andrew Cooper
2020-05-20 21:30 ` Andrew Cooper
2020-05-21 8:45 ` Roger Pau Monné
2020-05-21 16:27 ` Andrew Cooper [this message]
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