From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754281AbbGIVVm (ORCPT ); Thu, 9 Jul 2015 17:21:42 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:36755 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754040AbbGIVVY (ORCPT ); Thu, 9 Jul 2015 17:21:24 -0400 From: Duc Dang To: Bjorn Helgaas , Arnd Bergmann , Catalin Marinas , Ian Campbell , Pawel Moll , Rob Herring , Mark Rutland , Kumar Gala , Will Deacon , "David S. Miller" Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tanmay Inamdar , patches@apm.com, Duc Dang Subject: [PATCH v3 2/2] pci: xgene: Fix driver to handle multiple memory ranges Date: Thu, 9 Jul 2015 14:20:12 -0700 Message-Id: <844cb76fe55ce4ce45411281500bdb93e0d6932a.1436476100.git.dhdang@apm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: <1481643.dA4ocqzitg@wuerfel> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Gene PCIe controller has registers to support multiple memory ranges. This patch implement addtional register configuration required for the driver to support 1 additional huge 64-bit prefetch memory window. Signed-off-by: Duc Dang Signed-off-by: Tanmay Inamdar --- drivers/pci/host/pci-xgene.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c index a9dfb70..55fe865 100644 --- a/drivers/pci/host/pci-xgene.c +++ b/drivers/pci/host/pci-xgene.c @@ -321,8 +321,16 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, return ret; break; case IORESOURCE_MEM: - xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start, - res->start - window->offset); + if (res->flags & IORESOURCE_PREFETCH) + xgene_pcie_setup_ob_reg(port, res, OMR2BARL, + res->start, + res->start - + window->offset); + else + xgene_pcie_setup_ob_reg(port, res, OMR1BARL, + res->start, + res->start - + window->offset); break; case IORESOURCE_BUS: break; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: dhdang@apm.com (Duc Dang) Date: Thu, 9 Jul 2015 14:20:12 -0700 Subject: [PATCH v3 2/2] pci: xgene: Fix driver to handle multiple memory ranges In-Reply-To: References: Message-ID: <844cb76fe55ce4ce45411281500bdb93e0d6932a.1436476100.git.dhdang@apm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org X-Gene PCIe controller has registers to support multiple memory ranges. This patch implement addtional register configuration required for the driver to support 1 additional huge 64-bit prefetch memory window. Signed-off-by: Duc Dang Signed-off-by: Tanmay Inamdar --- drivers/pci/host/pci-xgene.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c index a9dfb70..55fe865 100644 --- a/drivers/pci/host/pci-xgene.c +++ b/drivers/pci/host/pci-xgene.c @@ -321,8 +321,16 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, return ret; break; case IORESOURCE_MEM: - xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start, - res->start - window->offset); + if (res->flags & IORESOURCE_PREFETCH) + xgene_pcie_setup_ob_reg(port, res, OMR2BARL, + res->start, + res->start - + window->offset); + else + xgene_pcie_setup_ob_reg(port, res, OMR1BARL, + res->start, + res->start - + window->offset); break; case IORESOURCE_BUS: break; -- 1.9.1