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27 Mar 2020 06:52:01 +0800 IronPort-SDR: Gl8/aWlWVWvUq5YR6iPwTzWhM6y6Q1iQy/emjgdRNi7P73uTLivSPWfJNL3iuDINdmEvFF07Fh 6fDB/bGhrn5HrfMLPAFWP7A8BFETFiDaCz85FAgWB0ABtJRii01IAOXFjwfz2aJr95hBgwze2Y evHno/l4F/tIjb+7hKmCJcEdapOYkQo3P5bNEduB5iHp50rshD1KHfDlppJZSRVfdeMjfU6fta 09s2bziHxHXfk6WophjSQaji9/G+/4XIsPeq+bSSpYrqzQU62Ia86BkWDtjmD7cSY4JsPdTV1T uTarp3oirRjBa2WCW0+punhL Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2020 15:42:47 -0700 IronPort-SDR: ys1GDTncR0JUslY5A5g6yJhRUHtj0+XpIwuJZI9ypaIYkGFHOGdV8BVhBKKJS5nqiC3XHUcXy0 9ffQCn/ljgGeHdMjsuO+LhC2vZltnb/Y+gW8K4nyzWzVY5/rAXf9STHWb9qRDXqEL4DHLE03EJ TSCCTw0chhkIJM3xvKQoFO2k0w2pyZOvhWda8VJBbqewntvzEW/6UxSMG2uglW+Q29c3nnQNdu YPYKZOsEvgmo/iKSBsHabU3ofWbLbry4MiLKSqRl9BiahRum1oTHyHAAK03gX1iKQTkKKfIpBt ULg= WDCIronportException: Internal Received: from 2j0d3g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.54.250]) by uls-op-cesaip01.wdc.com with ESMTP; 26 Mar 2020 15:51:45 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags Date: Thu, 26 Mar 2020 15:44:09 -0700 Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Take the result of stage-1 and stage-2 page table walks and AND the two protection flags together. This way we require both to set permissions instead of just stage-2. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f36d184b7b..50e13a064f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; - int prot; + int prot, prot2; bool pmp_violation = false; bool m_mode_two_stage = false; bool hs_mode_two_stage = false; @@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Second stage lookup */ im_address = pa; - ret = get_physical_address(env, &pa, &prot, im_address, + ret = get_physical_address(env, &pa, &prot2, im_address, access_type, mmu_idx, false, true); qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot); + __func__, im_address, ret, pa, prot2); + + prot &= prot2; if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && -- 2.26.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1jHbLs-0001Mc-6o for mharc-qemu-riscv@gnu.org; Thu, 26 Mar 2020 18:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59524) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jHbLq-0001I5-09 for qemu-riscv@nongnu.org; Thu, 26 Mar 2020 18:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jHbLo-0001Pn-Tb for qemu-riscv@nongnu.org; Thu, 26 Mar 2020 18:51:49 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:23243) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jHbLm-0001L2-GS; Thu, 26 Mar 2020 18:51:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1585263122; x=1616799122; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nu1k2YInD1z4OmhzuT9vF/dekBAG0pZjrUjpjyIB2mY=; b=Eqp9KWGJuBYNvSAd8Hce5eDGIPcINlnwpiwTESaVSv29HHVxd6ASJTxe gWtrK6mYtrsA1ge+ArAok5IbDBQdePBa8RJTOyjgMH8euSITm+RYM3AYM J03cZ+h5cQQKB3pukFnmZM2WhZiWubE1NrK9P9eSbW/WcRW8PBFM8Y8QD RChidVIdfsqdYRhhsGL1Fa0cn+JJThqsfo9JNoE0lVR1FDOY8d9dZAU4J 1IL0lnwxd2a/POM0sFmDuUHNIuusZQKIbmMbFL+X5nMluLLQh4Xzzf2Bf vNyIE5eu2NauyGclfSy6VTv/nR9vIZhKUXbKtEPLHxKw7UoZWqP02hncx g==; IronPort-SDR: Zd6M6TVWNoaTEOz+zH+ZPgbocRJFqeyy3KIbJgddv0EjODR9tCMBEN8dgXkBoi4gjm643470jH cWsG0DykkBKRwW/2l4psMyIozvYv8fdTONB6rSx1Kf5E9ZtFLgOCKgYJc0nG7zHYBHis3JDu52 hCUjUZykdy8GOOGfw+PyQ70u4PGkZi3uKfZH7vb26qLD6fI+adfNldx+GVRosho8xNoLse0QSB q3BiZL4rY/5MqOTaTDIyntortfQRIgeGXjIA8EMiK5lbilG/OZPtP1qSFU5Sh6/kj2PVERduUo CyU= X-IronPort-AV: E=Sophos;i="5.72,310,1580745600"; d="scan'208";a="235858180" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 27 Mar 2020 06:52:01 +0800 IronPort-SDR: Gl8/aWlWVWvUq5YR6iPwTzWhM6y6Q1iQy/emjgdRNi7P73uTLivSPWfJNL3iuDINdmEvFF07Fh 6fDB/bGhrn5HrfMLPAFWP7A8BFETFiDaCz85FAgWB0ABtJRii01IAOXFjwfz2aJr95hBgwze2Y evHno/l4F/tIjb+7hKmCJcEdapOYkQo3P5bNEduB5iHp50rshD1KHfDlppJZSRVfdeMjfU6fta 09s2bziHxHXfk6WophjSQaji9/G+/4XIsPeq+bSSpYrqzQU62Ia86BkWDtjmD7cSY4JsPdTV1T uTarp3oirRjBa2WCW0+punhL Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2020 15:42:47 -0700 IronPort-SDR: ys1GDTncR0JUslY5A5g6yJhRUHtj0+XpIwuJZI9ypaIYkGFHOGdV8BVhBKKJS5nqiC3XHUcXy0 9ffQCn/ljgGeHdMjsuO+LhC2vZltnb/Y+gW8K4nyzWzVY5/rAXf9STHWb9qRDXqEL4DHLE03EJ TSCCTw0chhkIJM3xvKQoFO2k0w2pyZOvhWda8VJBbqewntvzEW/6UxSMG2uglW+Q29c3nnQNdu YPYKZOsEvgmo/iKSBsHabU3ofWbLbry4MiLKSqRl9BiahRum1oTHyHAAK03gX1iKQTkKKfIpBt ULg= WDCIronportException: Internal Received: from 2j0d3g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.54.250]) by uls-op-cesaip01.wdc.com with ESMTP; 26 Mar 2020 15:51:45 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags Date: Thu, 26 Mar 2020 15:44:09 -0700 Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.143.124 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Mar 2020 22:51:51 -0000 Take the result of stage-1 and stage-2 page table walks and AND the two protection flags together. This way we require both to set permissions instead of just stage-2. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f36d184b7b..50e13a064f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; - int prot; + int prot, prot2; bool pmp_violation = false; bool m_mode_two_stage = false; bool hs_mode_two_stage = false; @@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Second stage lookup */ im_address = pa; - ret = get_physical_address(env, &pa, &prot, im_address, + ret = get_physical_address(env, &pa, &prot2, im_address, access_type, mmu_idx, false, true); qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot); + __func__, im_address, ret, pa, prot2); + + prot &= prot2; if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) && -- 2.26.0