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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 1 December 2022 20:43:12 GMT+03:00, Manivannan Sadhasivam wrote: >UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the >required register settings using the tables_hs_g4 struct instance. > >Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >index 97d0baa9bac3..269f96a0f752 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >@@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), > }; > >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { >+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), >+}; >+ > static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), >@@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > }; > >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), >+}; >+ > static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), >@@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > }; > >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { >+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), >+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), >+}; >+ > static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), >@@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { > .serdes = sm8150_ufsphy_hs_b_serdes, > .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), > }, >+ .tbls_hs_g4 = { >+ .tx = sm8150_ufsphy_hs_g4_tx, >+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), >+ .rx = sm8150_ufsphy_hs_g4_rx, >+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), >+ .pcs = sm8150_ufsphy_hs_g4_pcs, >+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), >+ }, > .clk_list = sdm845_ufs_phy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), > .vreg_list = qmp_phy_vreg_l, -- With best wishes Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7805C4321E for ; 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Mon, 05 Dec 2022 13:52:16 -0800 (PST) Date: Tue, 06 Dec 2022 00:52:11 +0300 From: Dmitry Baryshkov To: Manivannan Sadhasivam , martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org CC: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v4_07/23=5D_phy=3A_qcom-qmp-ufs?= =?US-ASCII?Q?=3A_Add_HS_G4_mode_support_to_SM8150_SoC?= User-Agent: K-9 Mail for Android In-Reply-To: <20221201174328.870152-8-manivannan.sadhasivam@linaro.org> References: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org> <20221201174328.870152-8-manivannan.sadhasivam@linaro.org> Message-ID: <84BEB11D-127C-4156-ACA4-5BF193AFF5E7@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 1 December 2022 20:43:12 GMT+03:00, Manivannan Sadhasivam wrote: >UFS PHY in SM8150 SoC is capable of operating at HS G4 mode=2E Hence, add= the >required register settings using the tables_hs_g4 struct instance=2E > >Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov >--- > drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec | 36 +++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec b/drivers/phy/qual= comm/phy-qcom-qmp-ufs=2Ec >index 97d0baa9bac3=2E=2E269f96a0f752 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs=2Ec >@@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_t= x[] =3D { > QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), > }; >=20 >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] =3D { >+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), >+}; >+ > static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), > QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), >@@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_r= x[] =3D { > QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), > }; >=20 >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] =3D { >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), >+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), >+}; >+ > static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), >@@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_p= cs[] =3D { > QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > }; >=20 >+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] =3D { >+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), >+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), >+}; >+ > static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { > QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), >@@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = =3D { > =2Eserdes =3D sm8150_ufsphy_hs_b_serdes, > =2Eserdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), > }, >+ =2Etbls_hs_g4 =3D { >+ =2Etx =3D sm8150_ufsphy_hs_g4_tx, >+ =2Etx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), >+ =2Erx =3D sm8150_ufsphy_hs_g4_rx, >+ =2Erx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), >+ =2Epcs =3D sm8150_ufsphy_hs_g4_pcs, >+ =2Epcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), >+ }, > =2Eclk_list =3D sdm845_ufs_phy_clk_l, > =2Enum_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), > =2Evreg_list =3D qmp_phy_vreg_l, --=20 With best wishes Dmitry