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boundary="===============2059661410035803025==" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" --===============2059661410035803025== Content-Type: multipart/alternative; boundary="Apple-Mail=_F357CE15-3AFC-4D68-86E3-684210B830CC" --Apple-Mail=_F357CE15-3AFC-4D68-86E3-684210B830CC Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On May 6, 2020, at 10:46 AM, Jean-Philippe Brucker = wrote: >=20 > Some SMMUv3 implementation embed the Perf Monitor Group Registers = (PMCG) > inside the first 64kB region of the SMMU. Since PMCG are managed by a > separate driver, this layout causes resource reservation conflicts > during boot. >=20 > To avoid this conflict, only reserve the MMIO region we actually use: > the first 0xe0 bytes of page 0 and the first 0xd0 bytes of page 1. > Although devm_ioremap() still works on full pages under the hood, this > way we benefit from resource conflict checks. >=20 > Signed-off-by: Jean-Philippe Brucker > --- > A nicer (and hopefully working) solution to the problem dicussed here: > = https://lore.kernel.org/linux-iommu/20200421155745.19815-1-jean-philippe@l= inaro.org/ > --- > drivers/iommu/arm-smmu-v3.c | 50 +++++++++++++++++++++++++++++++++---- > 1 file changed, 45 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > index 82508730feb7a1..fc85cdd5b62cca 100644 > --- a/drivers/iommu/arm-smmu-v3.c > +++ b/drivers/iommu/arm-smmu-v3.c > @@ -171,6 +171,9 @@ > #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 > #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc >=20 > +#define ARM_SMMU_PAGE0_REG_SZ 0xe0 > +#define ARM_SMMU_PAGE1_REG_SZ 0xd0 > + > /* Common MSI config fields */ > #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) > #define MSI_CFG2_SH GENMASK(5, 4) > @@ -628,6 +631,7 @@ struct arm_smmu_strtab_cfg { > struct arm_smmu_device { > struct device *dev; > void __iomem *base; > + void __iomem *page1; >=20 > #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) > #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) > @@ -733,11 +737,14 @@ static struct arm_smmu_option_prop = arm_smmu_options[] =3D { > static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset, > struct arm_smmu_device = *smmu) > { > - if ((offset > SZ_64K) && > - (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY)) > - offset -=3D SZ_64K; > + void __iomem *base =3D smmu->base; >=20 > - return smmu->base + offset; > + if (offset > SZ_64K) { > + offset -=3D SZ_64K; > + if (smmu->page1) > + base =3D smmu->page1; > + } > + return base + offset; > } >=20 > static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain = *dom) > @@ -4021,6 +4028,28 @@ err_reset_pci_ops: __maybe_unused; > return err; > } >=20 > +static void __iomem *arm_smmu_ioremap(struct device *dev, > + resource_size_t start, > + resource_size_t size) > +{ > + void __iomem *dest_ptr; > + struct resource *res; > + > + res =3D devm_request_mem_region(dev, start, size, = dev_name(dev)); > + if (!res) { > + dev_err(dev, "can't request SMMU region %pa\n", &start); > + return IOMEM_ERR_PTR(-EINVAL); > + } > + > + dest_ptr =3D devm_ioremap(dev, start, size); > + if (!dest_ptr) { > + dev_err(dev, "ioremap failed for SMMU region %pR\n", = res); > + devm_release_mem_region(dev, start, size); > + dest_ptr =3D IOMEM_ERR_PTR(-ENOMEM); > + } > + return dest_ptr; > +} > + > static int arm_smmu_device_probe(struct platform_device *pdev) > { > int irq, ret; > @@ -4056,10 +4085,21 @@ static int arm_smmu_device_probe(struct = platform_device *pdev) > } > ioaddr =3D res->start; >=20 > - smmu->base =3D devm_ioremap_resource(dev, res); > + /* > + * Only map what we need, because the IMPLEMENTATION DEFINED = registers > + * may be used for the PMCGs, which are reserved by the PMU = driver. > + */ > + smmu->base =3D arm_smmu_ioremap(dev, ioaddr, = ARM_SMMU_PAGE0_REG_SZ); > if (IS_ERR(smmu->base)) > return PTR_ERR(smmu->base); >=20 > + if (arm_smmu_resource_size(smmu) > SZ_64K) { > + smmu->page1 =3D arm_smmu_ioremap(dev, ioaddr + SZ_64K, > + ARM_SMMU_PAGE1_REG_SZ); > + if (IS_ERR(smmu->page1)) > + return PTR_ERR(smmu->page1); > + } > + > /* Interrupt lines */ >=20 > irq =3D platform_get_irq_byname_optional(pdev, "combined"); > =E2=80=94=20 > 2.26.2 >=20 Tested-by: Tuan Phan > --Apple-Mail=_F357CE15-3AFC-4D68-86E3-684210B830CC Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8

On May 6, 2020, at 10:46 = AM, Jean-Philippe Brucker <jean-philippe@linaro.org> wrote:

Some SMMUv3 implementat= ion embed the Perf Monitor Group Registers (PMCG)
inside the = first 64kB region of the SMMU. Since PMCG are managed by a
se= parate driver, this layout causes resource reservation conflicts
during boot.

To avoid this conflict, onl= y reserve the MMIO region we actually use:
the first 0xe0 byt= es of page 0 and the first 0xd0 bytes of page 1.
Although dev= m_ioremap() still works on full pages under the hood, this
wa= y we benefit from resource conflict checks.

Si= gned-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
---
A nicer (and hopefully working) solution to the problem dicussed h= ere:
https://lore.kernel.org= /linux-iommu/20200421155745.19815-1-jean-philippe@linaro.org/
---
drivers/iommu/arm-smmu-v3.c | 50 +++&#= 43;++++++++++++++&#= 43;++++++++++++++--= --
1 file changed, 45 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers= /iommu/arm-smmu-v3.c
index 82508730feb7a1..fc85cdd5b62cca 100= 644
--- a/drivers/iommu/arm-smmu-v3.c
++= ;+ b/drivers/iommu/arm-smmu-v3.c
@@ -171,6 +171,9 @@<= br class=3D""> #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2= 0xdc
<= br class=3D"">+#define ARM_SMMU_PAGE0_REG_SZ 0xe0
+#define ARM_SMMU_PAGE1= _REG_SZ 0xd0
+
/* Common MSI config fields */
#d= efine MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
#define MSI_CFG2_SH GENMASK(5, 4)
@@ -628,6 +631= ,7 @@ struct arm_smmu_strtab_cfg {
struct arm_smmu_device {<= br class=3D""> struct device= *dev;
v= oid __iomem *base;
+ voi= d __iomem <= span class=3D"Apple-tab-span" style=3D"white-space:pre"> *page1;

#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
#def= ine ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
@@ -733,11 +737,14 @@ s= tatic struct arm_smmu_option_prop arm_smmu_options[] =3D {
s= tatic inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,
= struct arm_smmu_device *smmu)
{- if ((offset > SZ_64K) &&
-    (smmu->op= tions & ARM_SMMU_OPT_PAGE0_REGS_ONLY))
- offset -=3D SZ_64K;
= 3; void __i= omem *base =3D smmu->base;

- return smmu->base += ; offset;
+ if (offset > SZ_64K) {
+ offset -=3D SZ_64K;
+ if (smmu->= ;page1)
+ = bas= e =3D smmu->page1;
+ }
+ return base + offset;
}

static struct arm_smmu_domain *to_s= mmu_domain(struct iommu_domain *dom)
@@ -4021,6 +4028,28 = @@ err_reset_pci_ops: __maybe_unused;
return err;
}

+static void __iomem *arm_smmu_ioremap(struct= device *dev,
+  =     resource_size_t start,
+      resource_size_t si= ze)
+{
+ void __iomem *dest_ptr;
= 3; struct r= esource *res;
+
+ res =3D devm_request_mem_region(= dev, start, size, dev_name(dev));
+ if (!res) {
+<= span class=3D"Apple-tab-span" style=3D"white-space:pre"> dev_err(dev, "ca= n't request SMMU region %pa\n", &start);
+ return IOMEM_ERR_PTR(-EINV= AL);
+ }
+
+ dest_ptr =3D devm_ioremap(dev,= start, size);
+ if (!dest_ptr) {
+ dev_err(dev, "ioremap failed f= or SMMU region %pR\n", res);
+ devm_release_mem_region(dev, start, size);=
+ = dest_ptr =3D IOMEM_ERR_PTR(-ENOMEM);
+ }
+ return dest_ptr;+}
+
static int arm_smmu_= device_probe(struct platform_device *pdev)
{
= int irq, r= et;
@@ -4056,10 +4085,21 @@ static int arm_smmu_device_pr= obe(struct platform_device *pdev)
}
ioaddr =3D res->start;

- smmu->base =3D devm_ioremap_resource(dev, res);
+ /*
+ * Only map what we need, because the IMPLEMENTATION DEFINED = registers
+ * may be used for the PMCGs, which are reserved by the = PMU driver.
+ */
+ smmu->base =3D arm_smmu_ioremap(dev, i= oaddr, ARM_SMMU_PAGE0_REG_SZ);
if (IS_ERR(smmu->base))
return PTR_ERR(sm= mu->base);

+ if (arm_smmu_resource_size(smmu) >= SZ_64K) {
+ smmu->page1 =3D arm_smmu_ioremap(dev, ioaddr + SZ_64K,
+ <= /span>      &nb= sp;ARM_SMMU_PAGE1_REG_SZ);
+ if (IS_ERR(smmu->page1))
+ return PTR_ERR(smmu->page1);=
+ }
+
/* Interrupt lines */
irq =3D platform_get_irq_byname_optional(pdev, "combined");=E2=80=94
2.26.2

<= /div>

Tested-by: Tuan Pha= n <tuanpha= n@os.amperecomputing.com>

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