* [PATCH 00/12] Convert WAR defines to config options
@ 2020-08-24 16:32 Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 01/12] MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option Thomas Bogendoerfer
` (13 more replies)
0 siblings, 14 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, linux-mips, linux-kernel, linux-serial
This patches convert workaround (WAR) defines into config options and
gets rid of mach-*/war.h files.
Thomas Bogendoerfer (12):
MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
MIPS: Convert R10000_LLSC_WAR info a config option
MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
MIPS: Get rid of BCM1250_M3_WAR
MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
MIPS: Remove mach-*/war.h
arch/mips/Kconfig | 80 +++++++++++++
arch/mips/cavium-octeon/setup.c | 2 +-
arch/mips/include/asm/futex.h | 4 +-
arch/mips/include/asm/llsc.h | 2 +-
arch/mips/include/asm/local.h | 4 +-
arch/mips/include/asm/mach-cavium-octeon/war.h | 27 -----
arch/mips/include/asm/mach-generic/war.h | 23 ----
arch/mips/include/asm/mach-ip22/war.h | 27 -----
arch/mips/include/asm/mach-ip27/war.h | 23 ----
arch/mips/include/asm/mach-ip28/war.h | 23 ----
arch/mips/include/asm/mach-ip30/war.h | 24 ----
arch/mips/include/asm/mach-ip32/war.h | 23 ----
arch/mips/include/asm/mach-malta/war.h | 23 ----
arch/mips/include/asm/mach-rc32434/war.h | 23 ----
arch/mips/include/asm/mach-rm/war.h | 27 -----
arch/mips/include/asm/mach-sibyte/war.h | 38 -------
arch/mips/include/asm/mach-tx49xx/war.h | 23 ----
arch/mips/include/asm/mipsregs.h | 4 +-
arch/mips/include/asm/war.h | 150 -------------------------
arch/mips/kernel/signal.c | 8 +-
arch/mips/kernel/syscall.c | 2 +-
arch/mips/mm/c-r4k.c | 17 +--
arch/mips/mm/page.c | 16 ++-
arch/mips/mm/tlbex.c | 8 +-
arch/mips/mm/uasm.c | 2 +-
drivers/tty/serial/sb1250-duart.c | 9 +-
26 files changed, 127 insertions(+), 485 deletions(-)
delete mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
delete mode 100644 arch/mips/include/asm/mach-generic/war.h
delete mode 100644 arch/mips/include/asm/mach-ip22/war.h
delete mode 100644 arch/mips/include/asm/mach-ip27/war.h
delete mode 100644 arch/mips/include/asm/mach-ip28/war.h
delete mode 100644 arch/mips/include/asm/mach-ip30/war.h
delete mode 100644 arch/mips/include/asm/mach-ip32/war.h
delete mode 100644 arch/mips/include/asm/mach-malta/war.h
delete mode 100644 arch/mips/include/asm/mach-rc32434/war.h
delete mode 100644 arch/mips/include/asm/mach-rm/war.h
delete mode 100644 arch/mips/include/asm/mach-sibyte/war.h
delete mode 100644 arch/mips/include/asm/mach-tx49xx/war.h
--
2.16.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 01/12] MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 02/12] MIPS: Convert R4600_V1_HIT_CACHEOP " Thomas Bogendoerfer
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 8 ++++++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 1 -
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 10 ----------
arch/mips/mm/c-r4k.c | 6 ++++--
15 files changed, 12 insertions(+), 24 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 99220e7e465e..90f8aa04e2ec 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -638,6 +638,7 @@ config SGI_IP22
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select WAR_R4600_V1_INDEX_ICACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -2607,6 +2608,13 @@ config MIPS_ASID_BITS_VARIABLE
config MIPS_CRC_SUPPORT
bool
+# R4600 erratum. Due to the lack of errata information the exact
+# technical details aren't known. I've experimentally found that disabling
+# interrupts during indexed I-cache flushes seems to be sufficient to deal
+# with the issue.
+config WAR_R4600_V1_INDEX_ICACHEOP
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 2421411b7636..1e01e2f20086 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index f0f4a35d0870..7614a1545d1c 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index b48eb4ac362d..3424c1e8a24f 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -12,7 +12,6 @@
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
-#define R4600_V1_INDEX_ICACHEOP_WAR 1
#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index ef3efce0094a..5a91a7564fb9 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 61cd67354829..0dc70d59909e 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index a1fa0c1f5300..9f5c3305674c 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index e77b9d1b6c96..ac933b9119bb 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d62d2ffe515e..12c6393b6f31 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index af430d26f713..62e04bea61b3 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index eca16d167c2f..fe3c17f38650 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -12,7 +12,6 @@
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 4755b6116807..d34f3c1d6741 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 445abb4eb769..eb0375da266a 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index e43f800e662d..3c8923692fca 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,16 +72,6 @@
#define DADDI_WAR 0
#endif
-/*
- * Another R4600 erratum. Due to the lack of errata information the exact
- * technical details aren't known. I've experimentally found that disabling
- * interrupts during indexed I-cache flushes seems to be sufficient to deal
- * with the issue.
- */
-#ifndef R4600_V1_INDEX_ICACHEOP_WAR
-#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
-#endif
-
/*
* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
*
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d25f74f..bf454da84a9b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -366,7 +366,8 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
else if (ic_lsize == 32) {
- if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
+ cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
@@ -394,7 +395,8 @@ static void r4k_blast_icache_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache = blast_icache16;
else if (ic_lsize == 32) {
- if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
+ cpu_is_r4600_v1_x())
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32;
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 02/12] MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 01/12] MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 03/12] MIPS: Convert R4600_V2_HIT_CACHEOP " Thomas Bogendoerfer
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 28 +++++++++++++++++++++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 1 -
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 31 --------------------------
arch/mips/mm/c-r4k.c | 2 +-
arch/mips/mm/page.c | 6 +++--
16 files changed, 33 insertions(+), 46 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 90f8aa04e2ec..4d3179b66456 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -639,6 +639,7 @@ config SGI_IP22
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
+ select WAR_R4600_V1_HIT_CACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -2615,6 +2616,33 @@ config MIPS_CRC_SUPPORT
config WAR_R4600_V1_INDEX_ICACHEOP
bool
+# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
+#
+# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
+# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
+# executed if there is no other dcache activity. If the dcache is
+# accessed for another instruction immeidately preceding when these
+# cache instructions are executing, it is possible that the dcache
+# tag match outputs used by these cache instructions will be
+# incorrect. These cache instructions should be preceded by at least
+# four instructions that are not any kind of load or store
+# instruction.
+#
+# This is not allowed: lw
+# nop
+# nop
+# nop
+# cache Hit_Writeback_Invalidate_D
+#
+# This is allowed: lw
+# nop
+# nop
+# nop
+# nop
+# cache Hit_Writeback_Invalidate_D
+config WAR_R4600_V1_HIT_CACHEOP
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1e01e2f20086..915ce0352c20 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 7614a1545d1c..44d14be2e1e5 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 3424c1e8a24f..9154c54d428a 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -12,7 +12,6 @@
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
-#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 5a91a7564fb9..e7c070c85b7c 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 0dc70d59909e..22d9f78bf552 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 9f5c3305674c..1400b030982e 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ac933b9119bb..f91f4eddce8f 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 12c6393b6f31..a4d5d0926e81 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 62e04bea61b3..82ce2d313eed 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index fe3c17f38650..192ec3358ad0 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -12,7 +12,6 @@
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index d34f3c1d6741..bf793d36c890 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index eb0375da266a..7da1a3ea54c7 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
-#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 3c8923692fca..d336a0e57093 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,37 +72,6 @@
#define DADDI_WAR 0
#endif
-/*
- * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
- *
- * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
- * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- * executed if there is no other dcache activity. If the dcache is
- * accessed for another instruction immeidately preceding when these
- * cache instructions are executing, it is possible that the dcache
- * tag match outputs used by these cache instructions will be
- * incorrect. These cache instructions should be preceded by at least
- * four instructions that are not any kind of load or store
- * instruction.
- *
- * This is not allowed: lw
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- *
- * This is allowed: lw
- * nop
- * nop
- * nop
- * nop
- * cache Hit_Writeback_Invalidate_D
- */
-#ifndef R4600_V1_HIT_CACHEOP_WAR
-#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
-#endif
-
-
/*
* Writeback and invalidate the primary cache dcache before DMA.
*
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bf454da84a9b..814a295a2df2 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -132,7 +132,7 @@ struct bcache_ops *bcops = &no_sc_ops;
do { \
if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
*(volatile unsigned long *)CKSEG1; \
- if (R4600_V1_HIT_CACHEOP_WAR) \
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
__asm__ __volatile__("nop;nop;nop;nop"); \
} while (0)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cd805b005509..ecad11f5c67c 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -250,7 +250,8 @@ static inline void build_clear_pref(u32 **buf, int off)
if (cpu_has_cache_cdex_s) {
uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
} else if (cpu_has_cache_cdex_p) {
- if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
+ cpu_is_r4600_v1_x()) {
uasm_i_nop(buf);
uasm_i_nop(buf);
uasm_i_nop(buf);
@@ -402,7 +403,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
if (cpu_has_cache_cdex_s) {
uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
} else if (cpu_has_cache_cdex_p) {
- if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
+ cpu_is_r4600_v1_x()) {
uasm_i_nop(buf);
uasm_i_nop(buf);
uasm_i_nop(buf);
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 03/12] MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 01/12] MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 02/12] MIPS: Convert R4600_V1_HIT_CACHEOP " Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 04/12] MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR Thomas Bogendoerfer
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 14 ++++++++++++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 5 -----
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 5 -----
arch/mips/include/asm/mach-sibyte/war.h | 2 --
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 15 ---------------
arch/mips/mm/c-r4k.c | 3 ++-
arch/mips/mm/page.c | 10 ++++++----
16 files changed, 22 insertions(+), 41 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4d3179b66456..3cbeca6da823 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -640,6 +640,7 @@ config SGI_IP22
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
select WAR_R4600_V1_HIT_CACHEOP
+ select WAR_R4600_V2_HIT_CACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -877,6 +878,7 @@ config SNI_RM
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select WAR_R4600_V2_HIT_CACHEOP
help
The SNI RM200/300/400 are MIPS-based machines manufactured by
Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP
config WAR_R4600_V1_HIT_CACHEOP
bool
+# Writeback and invalidate the primary cache dcache before DMA.
+#
+# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
+# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
+# operate correctly if the internal data cache refill buffer is empty. These
+# CACHE instructions should be separated from any potential data cache miss
+# by a load instruction to an uncached address to empty the response buffer."
+# (Revision 2.0 device errata from IDT available on https://www.idt.com/
+# in .pdf format.)
+config WAR_R4600_V2_HIT_CACHEOP
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 915ce0352c20..4bc396d0fdd9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 44d14be2e1e5..4d46a880b832 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 9154c54d428a..a5a1c41df74e 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -8,11 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP22_WAR_H
#define __ASM_MIPS_MACH_IP22_WAR_H
-/*
- * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e7c070c85b7c..5891d506cffd 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 22d9f78bf552..346fc567ebb3 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 1400b030982e..f887a0a53e18 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index f91f4eddce8f..980dbd34355c 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index a4d5d0926e81..29f56803e3e5 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 82ce2d313eed..749787bb6c8e 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 192ec3358ad0..aded634ccb01 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -8,11 +8,6 @@
#ifndef __ASM_MIPS_MACH_RM_WAR_H
#define __ASM_MIPS_MACH_RM_WAR_H
-/*
- * The RM200C seems to have been shipped only with V2.0 R4600s
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index bf793d36c890..78fd2ad4930b 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,8 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
-
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
#ifndef __ASSEMBLY__
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7da1a3ea54c7..0b1666e0391a 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
-#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d336a0e57093..37092c2c68e1 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,21 +72,6 @@
#define DADDI_WAR 0
#endif
-/*
- * Writeback and invalidate the primary cache dcache before DMA.
- *
- * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
- * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
- * operate correctly if the internal data cache refill buffer is empty. These
- * CACHE instructions should be separated from any potential data cache miss
- * by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on https://www.idt.com/
- * in .pdf format.)
- */
-#ifndef R4600_V2_HIT_CACHEOP_WAR
-#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
-#endif
-
/*
* Workaround for the Sibyte M3 errata the text of which can be found at
*
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 814a295a2df2..df09a3653c4f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -130,7 +130,8 @@ struct bcache_ops *bcops = &no_sc_ops;
#define R4600_HIT_CACHEOP_WAR_IMPL \
do { \
- if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
+ if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
+ cpu_is_r4600_v2_x()) \
*(volatile unsigned long *)CKSEG1; \
if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
__asm__ __volatile__("nop;nop;nop;nop"); \
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index ecad11f5c67c..504bc4047c4c 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -258,7 +258,8 @@ static inline void build_clear_pref(u32 **buf, int off)
uasm_i_nop(buf);
}
- if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+ cpu_is_r4600_v2_x())
uasm_i_lw(buf, ZERO, ZERO, AT);
uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -303,7 +304,7 @@ void build_clear_page(void)
else
uasm_i_ori(&buf, A2, A0, off);
- if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
@@ -411,7 +412,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
uasm_i_nop(buf);
}
- if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+ cpu_is_r4600_v2_x())
uasm_i_lw(buf, ZERO, ZERO, AT);
uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -455,7 +457,7 @@ void build_copy_page(void)
else
uasm_i_ori(&buf, A2, A0, off);
- if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 04/12] MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (2 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 03/12] MIPS: Convert R4600_V2_HIT_CACHEOP " Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 05/12] MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option Thomas Bogendoerfer
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/include/asm/mach-cavium-octeon/war.h | 2 --
arch/mips/include/asm/mach-generic/war.h | 2 --
arch/mips/include/asm/mach-ip22/war.h | 2 --
arch/mips/include/asm/mach-ip27/war.h | 2 --
arch/mips/include/asm/mach-ip28/war.h | 2 --
arch/mips/include/asm/mach-ip30/war.h | 2 --
arch/mips/include/asm/mach-ip32/war.h | 2 --
arch/mips/include/asm/mach-malta/war.h | 2 --
arch/mips/include/asm/mach-rc32434/war.h | 2 --
arch/mips/include/asm/mach-rm/war.h | 2 --
arch/mips/include/asm/mach-sibyte/war.h | 2 --
arch/mips/include/asm/mach-tx49xx/war.h | 2 --
arch/mips/include/asm/war.h | 35 --------------------------
13 files changed, 59 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 4bc396d0fdd9..5826fbf4d3a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,8 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 4d46a880b832..11b1f5e41af0 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index a5a1c41df74e..e47a7e186ed2 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 5891d506cffd..f3c5cc8ff2bc 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 346fc567ebb3..f867697a1793 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index f887a0a53e18..acda1ee3fb62 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,8 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 980dbd34355c..ca381798f6ab 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 29f56803e3e5..d22ca4a3ec72 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 1
-#define MIPS_CACHE_SYNC_WAR 1
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 749787bb6c8e..fccf25dcc26f 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 1
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index aded634ccb01..556e0223e60b 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 78fd2ad4930b..0e18f0753407 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,8 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 0b1666e0391a..7019ddc4c68d 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 0
-#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 1
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 37092c2c68e1..590bf2b16b33 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,41 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
-/*
- * Fill buffers not flushed on CACHE instructions
- *
- * Hit_Invalidate_I cacheops invalidate an icache line but the refill
- * for that line can get stale data from the fill buffer instead of
- * accessing memory if the previous icache miss was also to that line.
- *
- * Workaround: generate an icache refill from a different line
- *
- * Affects:
- * MIPS 4K RTL revision <3.0, PRID revision <4
- */
-#ifndef MIPS4K_ICACHE_REFILL_WAR
-#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
-#endif
-
-/*
- * Missing implicit forced flush of evictions caused by CACHE
- * instruction
- *
- * Evictions caused by a CACHE instructions are not forced on to the
- * bus. The BIU gives higher priority to fetches than to the data from
- * the eviction buffer and no collision detection is performed between
- * fetches and pending data from the eviction buffer.
- *
- * Workaround: Execute a SYNC instruction after the cache instruction
- *
- * Affects:
- * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
- * MIPS 20Kc RTL revision <4.0, PRID revision <?
- */
-#ifndef MIPS_CACHE_SYNC_WAR
-#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
-#endif
-
/*
* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
* the line which this instruction itself exists, the following
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 05/12] MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (3 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 04/12] MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 06/12] MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR " Thomas Bogendoerfer
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 9 +++++++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 1 -
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 11 -----------
arch/mips/mm/c-r4k.c | 6 +++---
15 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3cbeca6da823..7db9611d7800 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -890,6 +890,7 @@ config MACH_TX39XX
config MACH_TX49XX
bool "Toshiba TX49 series based machines"
+ select WAR_TX49XX_ICACHE_INDEX_INV
config MIKROTIK_RB532
bool "Mikrotik RB532 boards"
@@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP
config WAR_R4600_V2_HIT_CACHEOP
bool
+# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
+# the line which this instruction itself exists, the following
+# operation is not guaranteed."
+#
+# Workaround: do two phase flushing for Index_Invalidate_I
+config WAR_TX49XX_ICACHE_INDEX_INV
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 5826fbf4d3a2..1cb30485dc94 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 11b1f5e41af0..79530836cc79 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index e47a7e186ed2..35286ba3ec57 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index f3c5cc8ff2bc..a18293c16ade 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index f867697a1793..1a6092e5c7b3 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index acda1ee3fb62..031c7b9c5236 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,7 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ca381798f6ab..25552158fa3a 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d22ca4a3ec72..9b0803537bce 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index fccf25dcc26f..924b51b9a340 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 556e0223e60b..0536972b24c8 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 0e18f0753407..9e006fdcf38a 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7019ddc4c68d..9293c5f9ffb2 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define TX49XX_ICACHE_INDEX_INV_WAR 1
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 590bf2b16b33..7a69641de57b 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,17 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
-/*
- * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
- * the line which this instruction itself exists, the following
- * operation is not guaranteed."
- *
- * Workaround: do two phase flushing for Index_Invalidate_I
- */
-#ifndef TX49XX_ICACHE_INDEX_INV_WAR
-#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
-#endif
-
/*
* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
* opposes it being called that) where invalid instructions in the same
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index df09a3653c4f..4b12081f9843 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -239,7 +239,7 @@ static void r4k_blast_dcache_setup(void)
r4k_blast_dcache = blast_dcache128;
}
-/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
+/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
#define JUMP_TO_ALIGN(order) \
__asm__ __volatile__( \
"b\t1f\n\t" \
@@ -371,7 +371,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
- else if (TX49XX_ICACHE_INDEX_INV_WAR)
+ else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed;
else if (current_cpu_type() == CPU_LOONGSON2EF)
@@ -399,7 +399,7 @@ static void r4k_blast_icache_setup(void)
if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
cpu_is_r4600_v1_x())
r4k_blast_icache = blast_r4600_v1_icache32;
- else if (TX49XX_ICACHE_INDEX_INV_WAR)
+ else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
r4k_blast_icache = tx49_blast_icache32;
else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache = loongson2_blast_icache32;
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 06/12] MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (4 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 05/12] MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 07/12] MIPS: Convert R10000_LLSC_WAR info " Thomas Bogendoerfer
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 9 +++++++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 1 -
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 10 ----------
arch/mips/kernel/signal.c | 8 +++++++-
15 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7db9611d7800..c32f6160f854 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -568,6 +568,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_VPE_LOADER
select SYS_SUPPORTS_ZBOOT
select USE_OF
+ select WAR_ICACHE_REFILLS
select ZONE_DMA32 if 64BIT
help
This enables support for the MIPS Technologies Malta evaluation
@@ -756,6 +757,7 @@ config SGI_IP32
select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select WAR_ICACHE_REFILLS
help
If you want this kernel to run on SGI O2 workstation, say Y here.
@@ -2666,6 +2668,13 @@ config WAR_R4600_V2_HIT_CACHEOP
config WAR_TX49XX_ICACHE_INDEX_INV
bool
+# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
+# opposes it being called that) where invalid instructions in the same
+# I-cache line worth of instructions being fetched may case spurious
+# exceptions.
+config WAR_ICACHE_REFILLS
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1cb30485dc94..1061917152c6 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 79530836cc79..966f40aedf16 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 35286ba3ec57..99f6531e5b9b 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index a18293c16ade..d8dfa7258bea 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 1a6092e5c7b3..f252df761ec8 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 031c7b9c5236..58ff9ca345b7 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,7 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1
#else
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 25552158fa3a..ca3efe457ae0 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 9b0803537bce..b7827eb09375 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 924b51b9a340..b7827eb09375 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 0536972b24c8..fe04d059dd0c 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 9e006fdcf38a..7c376f6eee9b 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 9293c5f9ffb2..5768889c20a7 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 7a69641de57b..a0942821d67d 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,16 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
-/*
- * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
- * opposes it being called that) where invalid instructions in the same
- * I-cache line worth of instructions being fetched may case spurious
- * exceptions.
- */
-#ifndef ICACHE_REFILLS_WORKAROUND_WAR
-#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
-#endif
-
/*
* On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
* may cause ll / sc and lld / scd sequences to execute non-atomically.
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index a0262729cd4c..f44265025281 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -545,6 +545,12 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
return err ?: protected_restore_fp_context(sc);
}
+#ifdef CONFIG_WAR_ICACHE_REFILLS
+#define SIGMASK ~(cpu_icache_line_size()-1)
+#else
+#define SIGMASK ALMASK
+#endif
+
void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
size_t frame_size)
{
@@ -565,7 +571,7 @@ void __user *get_sigframe(struct ksignal *ksig, struct pt_regs *regs,
sp = sigsp(sp, ksig);
- return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? ~(cpu_icache_line_size()-1) : ALMASK));
+ return (void __user *)((sp - frame_size) & SIGMASK);
}
/*
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 07/12] MIPS: Convert R10000_LLSC_WAR info a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (5 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 06/12] MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR " Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 08/12] MIPS: Convert MIPS34K_MISSED_ITLB_WAR into " Thomas Bogendoerfer
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 8 ++++++++
arch/mips/include/asm/futex.h | 4 ++--
arch/mips/include/asm/llsc.h | 2 +-
arch/mips/include/asm/local.h | 4 ++--
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 5 -----
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 1 -
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 8 --------
arch/mips/kernel/syscall.c | 2 +-
arch/mips/mm/tlbex.c | 2 +-
19 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c32f6160f854..acb790b556a8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -669,6 +669,7 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select NUMA
help
@@ -704,6 +705,7 @@ config SGI_IP28
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
help
This is the SGI Indigo2 with R10000 processor. To compile a Linux
@@ -730,6 +732,7 @@ config SGI_IP30
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_SMP
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select ARC_MEMORY
help
@@ -2675,6 +2678,11 @@ config WAR_TX49XX_ICACHE_INDEX_INV
config WAR_ICACHE_REFILLS
bool
+# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
+# may cause ll / sc and lld / scd sequences to execute non-atomically.
+config WAR_R10000_LLSC
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 2bf8f6014579..d85248404c52 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -21,7 +21,7 @@
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
{ \
- if (cpu_has_llsc && R10000_LLSC_WAR) { \
+ if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
@@ -133,7 +133,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
- if (cpu_has_llsc && R10000_LLSC_WAR) {
+ if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h
index c49738bc3bda..ec09fe5d6d6c 100644
--- a/arch/mips/include/asm/llsc.h
+++ b/arch/mips/include/asm/llsc.h
@@ -28,7 +28,7 @@
* works around a bug present in R10000 CPUs prior to revision 3.0 that could
* cause ll-sc sequences to execute non-atomically.
*/
-#if R10000_LLSC_WAR
+#ifdef CONFIG_WAR_R10000_LLSC
# define __SC_BEQZ "beqzl "
#elif MIPS_ISA_REV >= 6
# define __SC_BEQZ "beqzc "
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index fef0fda8f82f..ecda7295ddcd 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -31,7 +31,7 @@ static __inline__ long local_add_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && R10000_LLSC_WAR) {
+ if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
unsigned long temp;
__asm__ __volatile__(
@@ -80,7 +80,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && R10000_LLSC_WAR) {
+ if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
unsigned long temp;
__asm__ __volatile__(
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1061917152c6..52be3785e3e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 966f40aedf16..2229c8377288 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 99f6531e5b9b..f10efe589f93 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index d8dfa7258bea..0a07cf6731c0 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index f252df761ec8..9fdc6425c22c 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 58ff9ca345b7..8a8ec5578083 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,11 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#ifdef CONFIG_CPU_R10000
-#define R10000_LLSC_WAR 1
-#else
-#define R10000_LLSC_WAR 0
-#endif
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ca3efe457ae0..9e8c0c2a4c26 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index b7827eb09375..76f7de21b7dd 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index b7827eb09375..76f7de21b7dd 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index fe04d059dd0c..dcb80b558321 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7c376f6eee9b..0cf25eea846f 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 5768889c20a7..8e572d7d2b6e 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,7 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index a0942821d67d..d405ecb78cbd 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,14 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
-/*
- * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
- * may cause ll / sc and lld / scd sequences to execute non-atomically.
- */
-#ifndef R10000_LLSC_WAR
-#error Check setting of R10000_LLSC_WAR for your platform
-#endif
-
/*
* 34K core erratum: "Problems Executing the TLBR Instruction"
*/
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index c333e5788664..2afa3eef486a 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -106,7 +106,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
if (unlikely(!access_ok((const void __user *)addr, 4)))
return -EINVAL;
- if (cpu_has_llsc && R10000_LLSC_WAR) {
+ if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
__asm__ __volatile__ (
" .set push \n"
" .set arch=r4000 \n"
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 14f8ba93367f..e931eb06af57 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -90,7 +90,7 @@ static inline int __maybe_unused bcm1250_m3_war(void)
static inline int __maybe_unused r10000_llsc_war(void)
{
- return R10000_LLSC_WAR;
+ return IS_ENABLED(CONFIG_WAR_R10000_LLSC);
}
static int use_bbit_insns(void)
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 08/12] MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (6 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 07/12] MIPS: Convert R10000_LLSC_WAR info " Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 09/12] MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS Thomas Bogendoerfer
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 4 ++++
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 2 --
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/mipsregs.h | 4 ++--
arch/mips/include/asm/war.h | 7 -------
15 files changed, 6 insertions(+), 22 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index acb790b556a8..7991a04274da 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS
config WAR_R10000_LLSC
bool
+# 34K core erratum: "Problems Executing the TLBR Instruction"
+config WAR_MIPS34K_MISSED_ITLB
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 52be3785e3e2..9aa4ea5522a9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
OCTEON_IS_MODEL(OCTEON_CN6XXX)
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 2229c8377288..4f25636661d5 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index f10efe589f93..09169cfbf932 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 0a07cf6731c0..1c81d5464235 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 9fdc6425c22c..ff66adbaaae5 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 8a8ec5578083..b00469a39835 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -7,6 +7,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 9e8c0c2a4c26..c57a9cd2e50b 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 76f7de21b7dd..73c9e6d84a8f 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 76f7de21b7dd..73c9e6d84a8f 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index dcb80b558321..c396a31706ac 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 0cf25eea846f..fa9bbc228dd7 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -24,6 +24,4 @@ extern int sb1250_m3_workaround_needed(void);
#endif
-#define MIPS34K_MISSED_ITLB_WAR 0
-
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 8e572d7d2b6e..7213d9334f3f 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1a03fdc2c74a..3a7379b8f31c 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2716,7 +2716,7 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
int res = 0;
__asm__ __volatile__(
@@ -2738,7 +2738,7 @@ static inline void tlb_read(void)
"tlbr\n\t"
".set reorder");
-#if MIPS34K_MISSED_ITLB_WAR
+#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
if ((res & _ULCAST_(1)))
__asm__ __volatile__(
" .set push \n"
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d405ecb78cbd..4f4d37b3dd07 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -93,11 +93,4 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
-/*
- * 34K core erratum: "Problems Executing the TLBR Instruction"
- */
-#ifndef MIPS34K_MISSED_ITLB_WAR
-#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
-#endif
-
#endif /* _ASM_WAR_H */
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 09/12] MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (7 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 08/12] MIPS: Convert MIPS34K_MISSED_ITLB_WAR into " Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 10/12] MIPS: Get rid of BCM1250_M3_WAR Thomas Bogendoerfer
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, linux-mips, linux-kernel, linux-serial
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/include/asm/mach-cavium-octeon/war.h | 1 -
arch/mips/include/asm/mach-generic/war.h | 1 -
arch/mips/include/asm/mach-ip22/war.h | 1 -
arch/mips/include/asm/mach-ip27/war.h | 1 -
arch/mips/include/asm/mach-ip28/war.h | 1 -
arch/mips/include/asm/mach-ip30/war.h | 1 -
arch/mips/include/asm/mach-ip32/war.h | 1 -
arch/mips/include/asm/mach-malta/war.h | 1 -
arch/mips/include/asm/mach-rc32434/war.h | 1 -
arch/mips/include/asm/mach-rm/war.h | 1 -
arch/mips/include/asm/mach-sibyte/war.h | 2 --
arch/mips/include/asm/mach-tx49xx/war.h | 1 -
arch/mips/include/asm/war.h | 7 -------
drivers/tty/serial/sb1250-duart.c | 9 ++++-----
14 files changed, 4 insertions(+), 25 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 9aa4ea5522a9..0a2bf6b7af94 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -10,7 +10,6 @@
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
OCTEON_IS_MODEL(OCTEON_CN6XXX)
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 4f25636661d5..6b7de91435e3 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -9,6 +9,5 @@
#define __ASM_MACH_GENERIC_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 09169cfbf932..70de6a5008d3 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_IP22_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 1c81d5464235..5b01e8fe245f 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_IP27_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index ff66adbaaae5..ba4267e2d34d 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_IP28_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index b00469a39835..f404e22b7798 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -6,6 +6,5 @@
#define __ASM_MIPS_MACH_IP30_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index c57a9cd2e50b..01475db746ec 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_IP32_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 73c9e6d84a8f..68b204ff59a6 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 73c9e6d84a8f..68b204ff59a6 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index c396a31706ac..093a3894ae41 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_RM_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index fa9bbc228dd7..71eff5bc3f53 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -15,12 +15,10 @@ extern int sb1250_m3_workaround_needed(void);
#endif
#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
-#define SIBYTE_1956_WAR 1
#else
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7213d9334f3f..0dc2beb5bf5a 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -9,6 +9,5 @@
#define __ASM_MIPS_MACH_TX49XX_WAR_H
#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 4f4d37b3dd07..2ce5cd61a072 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -86,11 +86,4 @@
#error Check setting of BCM1250_M3_WAR for your platform
#endif
-/*
- * This is a DUART workaround related to glitches around register accesses
- */
-#ifndef SIBYTE_1956_WAR
-#error Check setting of SIBYTE_1956_WAR for your platform
-#endif
-
#endif /* _ASM_WAR_H */
diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c
index bd5e7e9938ce..22c7bc90b104 100644
--- a/drivers/tty/serial/sb1250-duart.c
+++ b/drivers/tty/serial/sb1250-duart.c
@@ -35,7 +35,6 @@
#include <linux/refcount.h>
#include <asm/io.h>
-#include <asm/war.h>
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_uart.h>
@@ -157,7 +156,7 @@ static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
unsigned char retval;
retval = __read_sbdchn(sport, reg);
- if (SIBYTE_1956_WAR)
+ if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
__war_sbd1956(sport);
return retval;
}
@@ -167,7 +166,7 @@ static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
unsigned char retval;
retval = __read_sbdshr(sport, reg);
- if (SIBYTE_1956_WAR)
+ if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
__war_sbd1956(sport);
return retval;
}
@@ -175,14 +174,14 @@ static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
{
__write_sbdchn(sport, reg, value);
- if (SIBYTE_1956_WAR)
+ if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
__war_sbd1956(sport);
}
static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
{
__write_sbdshr(sport, reg, value);
- if (SIBYTE_1956_WAR)
+ if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
__war_sbd1956(sport);
}
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 10/12] MIPS: Get rid of BCM1250_M3_WAR
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (8 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 09/12] MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 11/12] MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR Thomas Bogendoerfer
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/include/asm/mach-cavium-octeon/war.h | 2 --
arch/mips/include/asm/mach-generic/war.h | 2 --
arch/mips/include/asm/mach-ip22/war.h | 2 --
arch/mips/include/asm/mach-ip27/war.h | 2 --
arch/mips/include/asm/mach-ip28/war.h | 2 --
arch/mips/include/asm/mach-ip30/war.h | 2 --
arch/mips/include/asm/mach-ip32/war.h | 2 --
arch/mips/include/asm/mach-malta/war.h | 2 --
arch/mips/include/asm/mach-rc32434/war.h | 2 --
arch/mips/include/asm/mach-rm/war.h | 2 --
arch/mips/include/asm/mach-sibyte/war.h | 14 --------------
arch/mips/include/asm/mach-tx49xx/war.h | 2 --
arch/mips/include/asm/war.h | 14 --------------
arch/mips/mm/tlbex.c | 6 +++++-
14 files changed, 5 insertions(+), 51 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 0a2bf6b7af94..616de70e697c 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,8 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define BCM1250_M3_WAR 0
-
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
OCTEON_IS_MODEL(OCTEON_CN6XXX)
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 6b7de91435e3..94796ad7e7de 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 70de6a5008d3..12cf05dd46d3 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_IP22_WAR_H
#define __ASM_MIPS_MACH_IP22_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 5b01e8fe245f..0852fe64594d 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index ba4267e2d34d..32796925700a 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index f404e22b7798..ea77545f5128 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,6 +5,4 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 01475db746ec..3e81408795b4 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 68b204ff59a6..0f5401c0e888 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 68b204ff59a6..0f5401c0e888 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 093a3894ae41..723c9de79ea1 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_RM_WAR_H
#define __ASM_MIPS_MACH_RM_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 71eff5bc3f53..157eca1be328 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,18 +8,4 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
-
-#ifndef __ASSEMBLY__
-extern int sb1250_m3_workaround_needed(void);
-#endif
-
-#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
-
-#else
-
-#define BCM1250_M3_WAR 0
-
-#endif
-
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 0dc2beb5bf5a..edf50e2bbb34 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,6 +8,4 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
-#define BCM1250_M3_WAR 0
-
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 2ce5cd61a072..c20c04855089 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,18 +72,4 @@
#define DADDI_WAR 0
#endif
-/*
- * Workaround for the Sibyte M3 errata the text of which can be found at
- *
- * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
- *
- * This will enable the use of a special TLB refill handler which does a
- * consistency check on the information in c0_badvaddr and c0_entryhi and
- * will just return and take the exception again if the information was
- * found to be inconsistent.
- */
-#ifndef BCM1250_M3_WAR
-#error Check setting of BCM1250_M3_WAR for your platform
-#endif
-
#endif /* _ASM_WAR_H */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e931eb06af57..a7521b8f7658 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -83,9 +83,13 @@ static inline int r4k_250MHZhwbug(void)
return 0;
}
+extern int sb1250_m3_workaround_needed(void);
+
static inline int __maybe_unused bcm1250_m3_war(void)
{
- return BCM1250_M3_WAR;
+ if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
+ return sb1250_m3_workaround_needed();
+ return 0;
}
static inline int __maybe_unused r10000_llsc_war(void)
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 11/12] MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (9 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 10/12] MIPS: Get rid of BCM1250_M3_WAR Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 12/12] MIPS: Remove mach-*/war.h Thomas Bogendoerfer
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/cavium-octeon/setup.c | 2 +-
arch/mips/include/asm/mach-cavium-octeon/war.h | 3 ---
arch/mips/mm/uasm.c | 2 +-
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 4f34d92b52f9..8a357cb068c2 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1126,7 +1126,7 @@ EXPORT_SYMBOL(prom_putchar);
void __init prom_free_prom_memory(void)
{
- if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
/* Check for presence of Core-14449 fix. */
u32 insn;
u32 *foo;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 616de70e697c..ba6df0a186e9 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,4 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
- OCTEON_IS_MODEL(OCTEON_CN6XXX)
-
#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index c56f129c9a4b..81dd226d6b6b 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -394,7 +394,7 @@ I_u2u1u3(_lddir)
void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
unsigned int c)
{
- if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
/*
* As per erratum Core-14449, replace prefetches 0-4,
* 6-24 with 'pref 28'.
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 12/12] MIPS: Remove mach-*/war.h
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (10 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 11/12] MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR Thomas Bogendoerfer
@ 2020-08-24 16:32 ` Thomas Bogendoerfer
2020-08-24 17:10 ` [PATCH 00/12] Convert WAR defines to config options Florian Fainelli
2020-09-09 12:10 ` Thomas Bogendoerfer
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 16:32 UTC (permalink / raw)
To: linux-mips, linux-kernel
After conversion of all WAR defines we can now remove all mach-*/war.h
files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/include/asm/mach-cavium-octeon/war.h | 12 ------------
arch/mips/include/asm/mach-generic/war.h | 11 -----------
arch/mips/include/asm/mach-ip22/war.h | 11 -----------
arch/mips/include/asm/mach-ip27/war.h | 11 -----------
arch/mips/include/asm/mach-ip28/war.h | 11 -----------
arch/mips/include/asm/mach-ip30/war.h | 8 --------
arch/mips/include/asm/mach-ip32/war.h | 11 -----------
arch/mips/include/asm/mach-malta/war.h | 11 -----------
arch/mips/include/asm/mach-rc32434/war.h | 11 -----------
arch/mips/include/asm/mach-rm/war.h | 11 -----------
arch/mips/include/asm/mach-sibyte/war.h | 11 -----------
arch/mips/include/asm/mach-tx49xx/war.h | 11 -----------
arch/mips/include/asm/war.h | 2 --
13 files changed, 132 deletions(-)
delete mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
delete mode 100644 arch/mips/include/asm/mach-generic/war.h
delete mode 100644 arch/mips/include/asm/mach-ip22/war.h
delete mode 100644 arch/mips/include/asm/mach-ip27/war.h
delete mode 100644 arch/mips/include/asm/mach-ip28/war.h
delete mode 100644 arch/mips/include/asm/mach-ip30/war.h
delete mode 100644 arch/mips/include/asm/mach-ip32/war.h
delete mode 100644 arch/mips/include/asm/mach-malta/war.h
delete mode 100644 arch/mips/include/asm/mach-rc32434/war.h
delete mode 100644 arch/mips/include/asm/mach-rm/war.h
delete mode 100644 arch/mips/include/asm/mach-sibyte/war.h
delete mode 100644 arch/mips/include/asm/mach-tx49xx/war.h
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
deleted file mode 100644
index ba6df0a186e9..000000000000
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
- */
-#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
-
-#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
deleted file mode 100644
index 94796ad7e7de..000000000000
--- a/arch/mips/include/asm/mach-generic/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_GENERIC_WAR_H
-#define __ASM_MACH_GENERIC_WAR_H
-
-#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
deleted file mode 100644
index 12cf05dd46d3..000000000000
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP22_WAR_H
-#define __ASM_MIPS_MACH_IP22_WAR_H
-
-#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
deleted file mode 100644
index 0852fe64594d..000000000000
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP27_WAR_H
-#define __ASM_MIPS_MACH_IP27_WAR_H
-
-#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
deleted file mode 100644
index 32796925700a..000000000000
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP28_WAR_H
-#define __ASM_MIPS_MACH_IP28_WAR_H
-
-#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
deleted file mode 100644
index ea77545f5128..000000000000
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP30_WAR_H
-#define __ASM_MIPS_MACH_IP30_WAR_H
-
-#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
deleted file mode 100644
index 3e81408795b4..000000000000
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP32_WAR_H
-#define __ASM_MIPS_MACH_IP32_WAR_H
-
-#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
deleted file mode 100644
index 0f5401c0e888..000000000000
--- a/arch/mips/include/asm/mach-malta/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
deleted file mode 100644
index 0f5401c0e888..000000000000
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
deleted file mode 100644
index 723c9de79ea1..000000000000
--- a/arch/mips/include/asm/mach-rm/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_RM_WAR_H
-#define __ASM_MIPS_MACH_RM_WAR_H
-
-#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
deleted file mode 100644
index 157eca1be328..000000000000
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
-#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-
-#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
deleted file mode 100644
index edf50e2bbb34..000000000000
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
-#define __ASM_MIPS_MACH_TX49XX_WAR_H
-
-#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index c20c04855089..21443f096238 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -9,8 +9,6 @@
#ifndef _ASM_WAR_H
#define _ASM_WAR_H
-#include <war.h>
-
/*
* Work around certain R4000 CPU errata (as implemented by GCC):
*
--
2.16.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 00/12] Convert WAR defines to config options
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (11 preceding siblings ...)
2020-08-24 16:32 ` [PATCH 12/12] MIPS: Remove mach-*/war.h Thomas Bogendoerfer
@ 2020-08-24 17:10 ` Florian Fainelli
2020-08-24 17:28 ` Thomas Bogendoerfer
2020-09-09 12:10 ` Thomas Bogendoerfer
13 siblings, 1 reply; 17+ messages in thread
From: Florian Fainelli @ 2020-08-24 17:10 UTC (permalink / raw)
To: Thomas Bogendoerfer, Greg Kroah-Hartman, Jiri Slaby, linux-mips,
linux-kernel, linux-serial
On 8/24/20 9:32 AM, Thomas Bogendoerfer wrote:
> This patches convert workaround (WAR) defines into config options and
> gets rid of mach-*/war.h files.
Most (all but octeon?) of those platforms are not particularly popular
or widespread, but is not this going to make it harder for distributions
and people doing CI by having an explosion in the number of
configurations to test?
--
Florian
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/12] Convert WAR defines to config options
2020-08-24 17:10 ` [PATCH 00/12] Convert WAR defines to config options Florian Fainelli
@ 2020-08-24 17:28 ` Thomas Bogendoerfer
2020-08-24 20:37 ` Florian Fainelli
0 siblings, 1 reply; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-08-24 17:28 UTC (permalink / raw)
To: Florian Fainelli
Cc: Greg Kroah-Hartman, Jiri Slaby, linux-mips, linux-kernel, linux-serial
On Mon, Aug 24, 2020 at 10:10:07AM -0700, Florian Fainelli wrote:
> On 8/24/20 9:32 AM, Thomas Bogendoerfer wrote:
> > This patches convert workaround (WAR) defines into config options and
> > gets rid of mach-*/war.h files.
>
> Most (all but octeon?) of those platforms are not particularly popular
> or widespread, but is not this going to make it harder for distributions
> and people doing CI by having an explosion in the number of
> configurations to test?
all options are only selected by arch/mips/Kconfig, so nothing should
change for any CI.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/12] Convert WAR defines to config options
2020-08-24 17:28 ` Thomas Bogendoerfer
@ 2020-08-24 20:37 ` Florian Fainelli
0 siblings, 0 replies; 17+ messages in thread
From: Florian Fainelli @ 2020-08-24 20:37 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: Greg Kroah-Hartman, Jiri Slaby, linux-mips, linux-kernel, linux-serial
On 8/24/20 10:28 AM, Thomas Bogendoerfer wrote:
> On Mon, Aug 24, 2020 at 10:10:07AM -0700, Florian Fainelli wrote:
>> On 8/24/20 9:32 AM, Thomas Bogendoerfer wrote:
>>> This patches convert workaround (WAR) defines into config options and
>>> gets rid of mach-*/war.h files.
>>
>> Most (all but octeon?) of those platforms are not particularly popular
>> or widespread, but is not this going to make it harder for distributions
>> and people doing CI by having an explosion in the number of
>> configurations to test?
>
> all options are only selected by arch/mips/Kconfig, so nothing should
> change for any CI.
OK, had missed that part, thanks.
--
Florian
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/12] Convert WAR defines to config options
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
` (12 preceding siblings ...)
2020-08-24 17:10 ` [PATCH 00/12] Convert WAR defines to config options Florian Fainelli
@ 2020-09-09 12:10 ` Thomas Bogendoerfer
13 siblings, 0 replies; 17+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-09 12:10 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, linux-mips, linux-kernel, linux-serial
On Mon, Aug 24, 2020 at 06:32:42PM +0200, Thomas Bogendoerfer wrote:
> This patches convert workaround (WAR) defines into config options and
> gets rid of mach-*/war.h files.
>
> Thomas Bogendoerfer (12):
> MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
> MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
> MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
> MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
> MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
> MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
> MIPS: Convert R10000_LLSC_WAR info a config option
> MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
> MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
> MIPS: Get rid of BCM1250_M3_WAR
> MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
> MIPS: Remove mach-*/war.h
>
> arch/mips/Kconfig | 80 +++++++++++++
> arch/mips/cavium-octeon/setup.c | 2 +-
> arch/mips/include/asm/futex.h | 4 +-
> arch/mips/include/asm/llsc.h | 2 +-
> arch/mips/include/asm/local.h | 4 +-
> arch/mips/include/asm/mach-cavium-octeon/war.h | 27 -----
> arch/mips/include/asm/mach-generic/war.h | 23 ----
> arch/mips/include/asm/mach-ip22/war.h | 27 -----
> arch/mips/include/asm/mach-ip27/war.h | 23 ----
> arch/mips/include/asm/mach-ip28/war.h | 23 ----
> arch/mips/include/asm/mach-ip30/war.h | 24 ----
> arch/mips/include/asm/mach-ip32/war.h | 23 ----
> arch/mips/include/asm/mach-malta/war.h | 23 ----
> arch/mips/include/asm/mach-rc32434/war.h | 23 ----
> arch/mips/include/asm/mach-rm/war.h | 27 -----
> arch/mips/include/asm/mach-sibyte/war.h | 38 -------
> arch/mips/include/asm/mach-tx49xx/war.h | 23 ----
> arch/mips/include/asm/mipsregs.h | 4 +-
> arch/mips/include/asm/war.h | 150 -------------------------
> arch/mips/kernel/signal.c | 8 +-
> arch/mips/kernel/syscall.c | 2 +-
> arch/mips/mm/c-r4k.c | 17 +--
> arch/mips/mm/page.c | 16 ++-
> arch/mips/mm/tlbex.c | 8 +-
> arch/mips/mm/uasm.c | 2 +-
> drivers/tty/serial/sb1250-duart.c | 9 +-
> 26 files changed, 127 insertions(+), 485 deletions(-)
> delete mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
> delete mode 100644 arch/mips/include/asm/mach-generic/war.h
> delete mode 100644 arch/mips/include/asm/mach-ip22/war.h
> delete mode 100644 arch/mips/include/asm/mach-ip27/war.h
> delete mode 100644 arch/mips/include/asm/mach-ip28/war.h
> delete mode 100644 arch/mips/include/asm/mach-ip30/war.h
> delete mode 100644 arch/mips/include/asm/mach-ip32/war.h
> delete mode 100644 arch/mips/include/asm/mach-malta/war.h
> delete mode 100644 arch/mips/include/asm/mach-rc32434/war.h
> delete mode 100644 arch/mips/include/asm/mach-rm/war.h
> delete mode 100644 arch/mips/include/asm/mach-sibyte/war.h
> delete mode 100644 arch/mips/include/asm/mach-tx49xx/war.h
series applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-09-09 14:11 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-24 16:32 [PATCH 00/12] Convert WAR defines to config options Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 01/12] MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 02/12] MIPS: Convert R4600_V1_HIT_CACHEOP " Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 03/12] MIPS: Convert R4600_V2_HIT_CACHEOP " Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 04/12] MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 05/12] MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 06/12] MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR " Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 07/12] MIPS: Convert R10000_LLSC_WAR info " Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 08/12] MIPS: Convert MIPS34K_MISSED_ITLB_WAR into " Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 09/12] MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 10/12] MIPS: Get rid of BCM1250_M3_WAR Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 11/12] MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR Thomas Bogendoerfer
2020-08-24 16:32 ` [PATCH 12/12] MIPS: Remove mach-*/war.h Thomas Bogendoerfer
2020-08-24 17:10 ` [PATCH 00/12] Convert WAR defines to config options Florian Fainelli
2020-08-24 17:28 ` Thomas Bogendoerfer
2020-08-24 20:37 ` Florian Fainelli
2020-09-09 12:10 ` Thomas Bogendoerfer
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