From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Gonzalez Subject: Re: WIP: PCIe on MSM8998 Date: Wed, 27 Mar 2019 18:05:43 +0100 Message-ID: <851f14df-57de-209b-1a8c-c71eabec9d2c@free.fr> References: <6041e92f-4dbf-c6ce-d92a-220fc8239acb@free.fr> <2e7d4564-01ea-d0bc-51c8-2bc2c116c4cc@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <2e7d4564-01ea-d0bc-51c8-2bc2c116c4cc-5wv7dgnIgG8@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Robin Murphy , Lorenzo Pieralisi , Bjorn Helgaas , Joerg Roedel , Rob Clark Cc: Jeffrey Hugo , MSM , Douglas Anderson , Evan Green , Bjorn Andersson , iommu , Stanimir Varbanov , PCI , Lee Jones List-Id: linux-arm-msm@vger.kernel.org On 21/03/2019 00:07, Robin Murphy wrote: > Unfortunately, having looked around the code, I think I do. 4.4 long > predates the iommu-map binding, and in the absence of anything other > than the hard-coded SID==RID assumption of arm-smmu at the time, they > apparently went and did their own wacky thing[1]. AFAICS the Stream ID > appears to be pretty much derived from the PCI topology as I would hope, > but it looks like it might depend on some sort of lookup table being > programmed appropriately as well. > > Bear in mind that the this is _The Qualcomm Android Kernel_ we're trying > to reason about here - playing true to the stereotype, the diff against > the mainline driver is significantly bigger than the entire mainline > driver itself; the line count of arm-smmu.c alone is pushing > 2-and-a-half times that of the file in 4.4.y ;) > > Since the curiosity had set in, I finally got round to dumping the ACPI > tables from my Snapdragon 835 laptop, and judging by the IORT it seems > like the EFI firmware for Windows machines does provide some set of > static ID mappings which could probably transcribe to an iommu-map (if > indeed it's valid at all - Windows itself doesn't seem to be even > touching PCI here), but I guess the Android BSP might not be so > generous. That'll be a question for the Qualcomm folks. FWIW mine > interestingly claims that its SMMU instances are all sharing SPI 231 as > a global fault interrupt, but whether that's true and/or depends on the > runtime firmware, again I really have no idea. > > Robin. > > [1] > https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/pci/host/pci-msm.c?h=LE.UM.1.3.r3.25&id=f1fa301f977f06dcf990c0452d85e2f67d8cbbf1#n4687 It works at last! In the root complex DT node, I have: iommu-map = <0 &anoc1_smmu 0x1480 0x10000>; iommu-map-mask = <0>; AFAIU, this means: "map every Requester ID onto stream ID 0x1480" AFAIU, there is only a single end-point on the system: RID 0x100 As you pointed out Robin, we also need to set up some kind of lookup table: writel(0x100, pcie->parf + PCIE_0_PCIE20_PARF_BDF_TRANSLATE_n); AFAIU, this means: "RID 0x100 <-> stream ID 0x1480" (???) Is this good enough for mainline? Regards. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7482BC43381 for ; Wed, 27 Mar 2019 17:05:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 45B852082F for ; Wed, 27 Mar 2019 17:05:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727369AbfC0RFq (ORCPT ); Wed, 27 Mar 2019 13:05:46 -0400 Received: from ns.iliad.fr ([212.27.33.1]:35790 "EHLO ns.iliad.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727357AbfC0RFq (ORCPT ); Wed, 27 Mar 2019 13:05:46 -0400 Received: from ns.iliad.fr (localhost [127.0.0.1]) by ns.iliad.fr (Postfix) with ESMTP id C1ADA20631; Wed, 27 Mar 2019 18:05:43 +0100 (CET) Received: from [192.168.108.8] (freebox.vlq16.iliad.fr [213.36.7.13]) by ns.iliad.fr (Postfix) with ESMTP id A2C0A1FF74; Wed, 27 Mar 2019 18:05:43 +0100 (CET) Subject: Re: WIP: PCIe on MSM8998 To: Robin Murphy , Lorenzo Pieralisi , Bjorn Helgaas , Joerg Roedel , Rob Clark Cc: MSM , PCI , Jeffrey Hugo , Bjorn Andersson , Lee Jones , Evan Green , Douglas Anderson , Stanimir Varbanov , Vivek Gautam , iommu References: <6041e92f-4dbf-c6ce-d92a-220fc8239acb@free.fr> <2e7d4564-01ea-d0bc-51c8-2bc2c116c4cc@arm.com> From: Marc Gonzalez Message-ID: <851f14df-57de-209b-1a8c-c71eabec9d2c@free.fr> Date: Wed, 27 Mar 2019 18:05:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <2e7d4564-01ea-d0bc-51c8-2bc2c116c4cc@arm.com> Content-Type: text/plain; charset=iso-8859-15 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV using ClamSMTP ; ns.iliad.fr ; Wed Mar 27 18:05:43 2019 +0100 (CET) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 21/03/2019 00:07, Robin Murphy wrote: > Unfortunately, having looked around the code, I think I do. 4.4 long > predates the iommu-map binding, and in the absence of anything other > than the hard-coded SID==RID assumption of arm-smmu at the time, they > apparently went and did their own wacky thing[1]. AFAICS the Stream ID > appears to be pretty much derived from the PCI topology as I would hope, > but it looks like it might depend on some sort of lookup table being > programmed appropriately as well. > > Bear in mind that the this is _The Qualcomm Android Kernel_ we're trying > to reason about here - playing true to the stereotype, the diff against > the mainline driver is significantly bigger than the entire mainline > driver itself; the line count of arm-smmu.c alone is pushing > 2-and-a-half times that of the file in 4.4.y ;) > > Since the curiosity had set in, I finally got round to dumping the ACPI > tables from my Snapdragon 835 laptop, and judging by the IORT it seems > like the EFI firmware for Windows machines does provide some set of > static ID mappings which could probably transcribe to an iommu-map (if > indeed it's valid at all - Windows itself doesn't seem to be even > touching PCI here), but I guess the Android BSP might not be so > generous. That'll be a question for the Qualcomm folks. FWIW mine > interestingly claims that its SMMU instances are all sharing SPI 231 as > a global fault interrupt, but whether that's true and/or depends on the > runtime firmware, again I really have no idea. > > Robin. > > [1] > https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/pci/host/pci-msm.c?h=LE.UM.1.3.r3.25&id=f1fa301f977f06dcf990c0452d85e2f67d8cbbf1#n4687 It works at last! In the root complex DT node, I have: iommu-map = <0 &anoc1_smmu 0x1480 0x10000>; iommu-map-mask = <0>; AFAIU, this means: "map every Requester ID onto stream ID 0x1480" AFAIU, there is only a single end-point on the system: RID 0x100 As you pointed out Robin, we also need to set up some kind of lookup table: writel(0x100, pcie->parf + PCIE_0_PCIE20_PARF_BDF_TRANSLATE_n); AFAIU, this means: "RID 0x100 <-> stream ID 0x1480" (???) Is this good enough for mainline? Regards.