From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933227AbcA0Od6 (ORCPT ); Wed, 27 Jan 2016 09:33:58 -0500 Received: from mail-bl2nam02on0070.outbound.protection.outlook.com ([104.47.38.70]:7680 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932555AbcA0Ody convert rfc822-to-8bit (ORCPT ); Wed, 27 Jan 2016 09:33:54 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Bharat Kumar Gogada To: Arnd Bergmann CC: "bhelgaas@google.com" , Michal Simek , "lorenzo.pieralisi@arm.com" , "paul.burton@imgtec.com" , "yinghai@kernel.org" , "wangyijing@huawei.com" , "robh@kernel.org" , "russell.joyce@york.ac.uk" , Soren Brinkmann , "jiang.liu@linux.intel.com" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Ravikiran Gummaluri Subject: RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Thread-Topic: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Thread-Index: AQHRTV/L8+mymSE9NEWCKEIBcVWY0J737/aAgBeS8pA= Date: Wed, 27 Jan 2016 14:33:45 +0000 Message-ID: <8520D5D51A55D047800579B09414719825873DA8@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.97.131] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22092.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(24454002)(189002)(199003)(50466002)(54356999)(5001960100002)(2920100001)(106466001)(4001430100002)(3846002)(2950100001)(1220700001)(102836003)(6806005)(107886002)(23726003)(110136002)(11100500001)(189998001)(50986999)(106116001)(6116002)(2900100001)(1096002)(586003)(5008740100001)(76176999)(81156007)(5003600100002)(19580395003)(47776003)(33656002)(63266004)(19580405001)(46406003)(97756001)(87936001)(55846006)(4326007)(86362001)(5004730100002)(5250100002)(92566002)(2906002)(107986001)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT212;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: c75796d4-490a-4476-bb6a-08d32726df87 X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT212;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: <5a61443353cc4502a1e8aa88b137eac4@CY1NAM02HT212.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13018025)(8121501046)(13015025)(13024025)(5005006)(13017025)(13023025)(10201501046)(3002001);SRVR:CY1NAM02HT212;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT212; X-Forefront-PRVS: 0834BAF534 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2016 14:33:49.2764 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT212 X-OriginatorOrg: xilinx.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver > to work on both Zynq and Microblaze > > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three unrelated > things here. > Agreed, will send as different patches in next series. > > --- > > --- a/drivers/pci/host/pcie-xilinx.c > > +++ b/drivers/pci/host/pcie-xilinx.c > > @@ -92,7 +92,12 @@ > > #define ECAM_DEV_NUM_SHIFT 12 > > > > /* Number of MSI IRQs */ > > -#define XILINX_NUM_MSI_IRQS 128 > > +#define XILINX_NUM_MSI_IRQS 128 > > +#ifdef CONFIG_ARM > > +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > > +#else > > +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > > +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? > > > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int > irq) > > */ > > static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { > > + int irq; > > int pos; > > > > pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); > > - if (pos < XILINX_NUM_MSI_IRQS) > > + irq = pos; > > +#ifdef CONFIG_MICROBLAZE > > + irq = XILINX_NUM_MSI_IRQS + pos; > > +#endif > > > if (IS_ENABLED(CONFIG_MICROBLAZE)) > irq = XILINX_NUM_MSI_IRQS + pos; > Agreed. > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct > > platform_device *pdev) #endif > > pci_scan_child_bus(bus); > > pci_assign_unassigned_bus_resources(bus); > > +#ifdef CONFIG_ARM > > pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > > +#endif > > pci_bus_add_devices(bus); > > platform_set_drvdata(pdev, port); > > Here it looks like microblaze gets it right. I'm not sure why we still need the > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in > common code. In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately. Bharat From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bharat Kumar Gogada Subject: RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Wed, 27 Jan 2016 14:33:45 +0000 Message-ID: <8520D5D51A55D047800579B09414719825873DA8@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Arnd Bergmann Cc: "bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org" , Michal Simek , "lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org" , "paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org" , "yinghai-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "wangyijing-hv44wF8Li93QT0dZR+AlfA@public.gmane.org" , "robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "russell.joyce-3oYoeGyd3e21Qrn1Bg8BZw@public.gmane.org" , Soren Brinkmann , "jiang.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org" , "pawel.moll-5wv7dgnIgG8@public.gmane.org" , "mark.rutland-5wv7dgnIgG8@public.gmane.org" , "ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org" , "galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , linux-p List-Id: devicetree@vger.kernel.org > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver > to work on both Zynq and Microblaze > > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three unrelated > things here. > Agreed, will send as different patches in next series. > > --- > > --- a/drivers/pci/host/pcie-xilinx.c > > +++ b/drivers/pci/host/pcie-xilinx.c > > @@ -92,7 +92,12 @@ > > #define ECAM_DEV_NUM_SHIFT 12 > > > > /* Number of MSI IRQs */ > > -#define XILINX_NUM_MSI_IRQS 128 > > +#define XILINX_NUM_MSI_IRQS 128 > > +#ifdef CONFIG_ARM > > +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > > +#else > > +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > > +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? > > > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int > irq) > > */ > > static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { > > + int irq; > > int pos; > > > > pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); > > - if (pos < XILINX_NUM_MSI_IRQS) > > + irq = pos; > > +#ifdef CONFIG_MICROBLAZE > > + irq = XILINX_NUM_MSI_IRQS + pos; > > +#endif > > > if (IS_ENABLED(CONFIG_MICROBLAZE)) > irq = XILINX_NUM_MSI_IRQS + pos; > Agreed. > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct > > platform_device *pdev) #endif > > pci_scan_child_bus(bus); > > pci_assign_unassigned_bus_resources(bus); > > +#ifdef CONFIG_ARM > > pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > > +#endif > > pci_bus_add_devices(bus); > > platform_set_drvdata(pdev, port); > > Here it looks like microblaze gets it right. I'm not sure why we still need the > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in > common code. In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately. Bharat -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Bharat Kumar Gogada To: Arnd Bergmann CC: "bhelgaas@google.com" , Michal Simek , "lorenzo.pieralisi@arm.com" , "paul.burton@imgtec.com" , "yinghai@kernel.org" , "wangyijing@huawei.com" , "robh@kernel.org" , "russell.joyce@york.ac.uk" , Soren Brinkmann , "jiang.liu@linux.intel.com" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Ravikiran Gummaluri Subject: RE: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Wed, 27 Jan 2016 14:33:45 +0000 Message-ID: <8520D5D51A55D047800579B09414719825873DA8@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver > to work on both Zynq and Microblaze > > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three unrelated > things here. > Agreed, will send as different patches in next series. > > --- > > --- a/drivers/pci/host/pcie-xilinx.c > > +++ b/drivers/pci/host/pcie-xilinx.c > > @@ -92,7 +92,12 @@ > > #define ECAM_DEV_NUM_SHIFT 12 > > > > /* Number of MSI IRQs */ > > -#define XILINX_NUM_MSI_IRQS 128 > > +#define XILINX_NUM_MSI_IRQS 128 > > +#ifdef CONFIG_ARM > > +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > > +#else > > +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > > +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? > > > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int > irq) > > */ > > static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { > > + int irq; > > int pos; > > > > pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); > > - if (pos < XILINX_NUM_MSI_IRQS) > > + irq = pos; > > +#ifdef CONFIG_MICROBLAZE > > + irq = XILINX_NUM_MSI_IRQS + pos; > > +#endif > > > if (IS_ENABLED(CONFIG_MICROBLAZE)) > irq = XILINX_NUM_MSI_IRQS + pos; > Agreed. > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct > > platform_device *pdev) #endif > > pci_scan_child_bus(bus); > > pci_assign_unassigned_bus_resources(bus); > > +#ifdef CONFIG_ARM > > pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > > +#endif > > pci_bus_add_devices(bus); > > platform_set_drvdata(pdev, port); > > Here it looks like microblaze gets it right. I'm not sure why we still need the > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in > common code. In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately. Bharat From mboxrd@z Thu Jan 1 00:00:00 1970 From: bharat.kumar.gogada@xilinx.com (Bharat Kumar Gogada) Date: Wed, 27 Jan 2016 14:33:45 +0000 Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> Message-ID: <8520D5D51A55D047800579B09414719825873DA8@XAP-PVEXMBX01.xlnx.xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver > to work on both Zynq and Microblaze > > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three unrelated > things here. > Agreed, will send as different patches in next series. > > --- > > --- a/drivers/pci/host/pcie-xilinx.c > > +++ b/drivers/pci/host/pcie-xilinx.c > > @@ -92,7 +92,12 @@ > > #define ECAM_DEV_NUM_SHIFT 12 > > > > /* Number of MSI IRQs */ > > -#define XILINX_NUM_MSI_IRQS 128 > > +#define XILINX_NUM_MSI_IRQS 128 > > +#ifdef CONFIG_ARM > > +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS > > +#else > > +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) > > +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? > > > @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int > irq) > > */ > > static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { > > + int irq; > > int pos; > > > > pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); > > - if (pos < XILINX_NUM_MSI_IRQS) > > + irq = pos; > > +#ifdef CONFIG_MICROBLAZE > > + irq = XILINX_NUM_MSI_IRQS + pos; > > +#endif > > > if (IS_ENABLED(CONFIG_MICROBLAZE)) > irq = XILINX_NUM_MSI_IRQS + pos; > Agreed. > > @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct > > platform_device *pdev) #endif > > pci_scan_child_bus(bus); > > pci_assign_unassigned_bus_resources(bus); > > +#ifdef CONFIG_ARM > > pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > > +#endif > > pci_bus_add_devices(bus); > > platform_set_drvdata(pdev, port); > > Here it looks like microblaze gets it right. I'm not sure why we still need the > pci_fixup_irqs() on ARM, but my feeling is that this should be fixed in > common code. In arm pci_fixup_irqs is called by pci_common_init_dev (arch/arm/kernel/bios32.c), since this API is removed now, I was calling it separately. Bharat