From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756841AbcBJF4A (ORCPT ); Wed, 10 Feb 2016 00:56:00 -0500 Received: from mail-cys01nam02on0065.outbound.protection.outlook.com ([104.47.37.65]:64934 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752126AbcBJFz5 (ORCPT ); Wed, 10 Feb 2016 00:55:57 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Bharat Kumar Gogada To: Paul Burton CC: "bhelgaas@google.com" , Michal Simek , "lorenzo.pieralisi@arm.com" , "yinghai@kernel.org" , "wangyijing@huawei.com" , "robh@kernel.org" , "russell.joyce@york.ac.uk" , Soren Brinkmann , "jiang.liu@linux.intel.com" , "arnd@arndb.de" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Ravikiran Gummaluri Subject: RE: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Thread-Topic: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Thread-Index: AQHRYyaIE2Tq7Il++k68bJn/MWC9ep8jXK0AgAFqLyA= Date: Wed, 10 Feb 2016 05:55:51 +0000 Message-ID: <8520D5D51A55D047800579B09414719825881780@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1455014518-8708-1-git-send-email-bharatku@xilinx.com> <1455014518-8708-4-git-send-email-bharatku@xilinx.com> <20160209161134.GA24244@NP-P-BURTON> In-Reply-To: <20160209161134.GA24244@NP-P-BURTON> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.96.57] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22120.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(24454002)(189002)(199003)(5001960100002)(6806005)(110136002)(107886002)(102836003)(87936001)(23676002)(92566002)(1220700001)(5003600100002)(5008740100001)(19580395003)(106466001)(19580405001)(5250100002)(5004730100002)(11100500001)(189998001)(55846006)(106116001)(50466002)(4001430100002)(33656002)(6116002)(2950100001)(63266004)(2920100001)(2900100001)(86362001)(1096002)(586003)(15975445007)(47776003)(76176999)(50986999)(54356999)(2906002)(3846002)(4326007)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT085;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 6c74f359-9f15-4978-f4ea-08d331ded7b5 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT085; X-Microsoft-Antispam-PRVS: <25d7595fcdfe4220bb48e1431719acd5@SN1NAM02HT085.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13018025)(13017025)(8121501046)(13024025)(13023025)(13015025)(5005006)(3002001)(10201501046);SRVR:SN1NAM02HT085;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT085; X-Forefront-PRVS: 0848C1A6AA X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2016 05:55:55.4492 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT085 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u1A5u7DB009420 > On Tue, Feb 09, 2016 at 04:11:56PM +0530, Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > --- > > Changes: > > Removed unneccessary architecture dependent number of MSI's. > > Added #ifdef to pci_fixup_irqs which is ARM specific API. > > Hi Bharat, > > Why do you say pci_fixup_irqs is ARM-specific? It's declared in > include/linux/pci.h, defined in drivers/pci/setup-irq.c & used by multiple > architectures (alpha, arm, m68k, mips, sh, sparc, tile, > unicore32 from a quick grep). > > Will you not break INTX-style interrupts by removing this? > I meant to say ARM specific w.r.t Microblaze architecture, which is what this patch series are for. This has been already discussed in my previous patch by Arnd Bergmann and Lorenzo Pieralisi . (https://lkml.org/lkml/2016/1/12/707) Bharat From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bharat Kumar Gogada Subject: RE: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Wed, 10 Feb 2016 05:55:51 +0000 Message-ID: <8520D5D51A55D047800579B09414719825881780@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1455014518-8708-1-git-send-email-bharatku@xilinx.com> <1455014518-8708-4-git-send-email-bharatku@xilinx.com> <20160209161134.GA24244@NP-P-BURTON> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20160209161134.GA24244@NP-P-BURTON> Content-Language: en-US Sender: linux-pci-owner@vger.kernel.org To: Paul Burton Cc: "bhelgaas@google.com" , Michal Simek , "lorenzo.pieralisi@arm.com" , "yinghai@kernel.org" , "wangyijing@huawei.com" , "robh@kernel.org" , "russell.joyce@york.ac.uk" , Soren Brinkmann , "jiang.liu@linux.intel.com" , "arnd@arndb.de" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , linux-pci@vger.kernel.org List-Id: devicetree@vger.kernel.org PiBPbiBUdWUsIEZlYiAwOSwgMjAxNiBhdCAwNDoxMTo1NlBNICswNTMwLCBCaGFyYXQgS3VtYXIg R29nYWRhIHdyb3RlOg0KPiA+IE1vZGlmeWluZyBYaWxpbnggQVhJIFBDSWUgSG9zdCBCcmlkZ2Ug U29mdCBJUCBkcml2ZXIgdG8gd29yayBvbiBib3RoDQo+ID4gWnlucSBhbmQgTWljcm9ibGF6ZSBB cmNoaXRlY3R1cmVzLg0KPiA+IFdpdGggdGhlc2UgbW9kaWZpY2F0aW9ucyBkcml2ZXJzL3BjaS9o b3N0L3BjaWUteGlsaW54LmMsIHdpbGwgd29yayBvbg0KPiA+IGJvdGggWnlucSBhbmQgTWljcm9i bGF6ZSBBcmNoaXRlY3R1cmVzLg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogQmhhcmF0IEt1bWFy IEdvZ2FkYSA8YmhhcmF0a3VAeGlsaW54LmNvbT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBSYXZpIEtp cmFuIEd1bW1hbHVyaSA8cmd1bW1hbEB4aWxpbnguY29tPg0KPiA+IC0tLQ0KPiA+IENoYW5nZXM6 DQo+ID4gUmVtb3ZlZCB1bm5lY2Nlc3NhcnkgYXJjaGl0ZWN0dXJlIGRlcGVuZGVudCBudW1iZXIg b2YgTVNJJ3MuDQo+ID4gQWRkZWQgI2lmZGVmIHRvIHBjaV9maXh1cF9pcnFzIHdoaWNoIGlzIEFS TSBzcGVjaWZpYyBBUEkuDQo+IA0KPiBIaSBCaGFyYXQsDQo+IA0KPiBXaHkgZG8geW91IHNheSBw Y2lfZml4dXBfaXJxcyBpcyBBUk0tc3BlY2lmaWM/IEl0J3MgZGVjbGFyZWQgaW4NCj4gaW5jbHVk ZS9saW51eC9wY2kuaCwgZGVmaW5lZCBpbiBkcml2ZXJzL3BjaS9zZXR1cC1pcnEuYyAmIHVzZWQg YnkgbXVsdGlwbGUNCj4gYXJjaGl0ZWN0dXJlcyAoYWxwaGEsIGFybSwgbTY4aywgbWlwcywgc2gs IHNwYXJjLCB0aWxlLA0KPiB1bmljb3JlMzIgZnJvbSBhIHF1aWNrIGdyZXApLg0KPiANCj4gV2ls bCB5b3Ugbm90IGJyZWFrIElOVFgtc3R5bGUgaW50ZXJydXB0cyBieSByZW1vdmluZyB0aGlzPw0K PiANCkkgbWVhbnQgdG8gc2F5IEFSTSBzcGVjaWZpYyB3LnIudCBNaWNyb2JsYXplIGFyY2hpdGVj dHVyZSwgd2hpY2ggaXMgd2hhdCB0aGlzIHBhdGNoIHNlcmllcyBhcmUgZm9yLiBUaGlzIGhhcyBi ZWVuIGFscmVhZHkgZGlzY3Vzc2VkIGluIG15IHByZXZpb3VzIHBhdGNoIGJ5ICBBcm5kIEJlcmdt YW5uIGFuZCBMb3JlbnpvIFBpZXJhbGlzaSAuIChodHRwczovL2xrbWwub3JnL2xrbWwvMjAxNi8x LzEyLzcwNykNCg0KQmhhcmF0DQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-cys01nam02on0065.outbound.protection.outlook.com ([104.47.37.65]:64934 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752126AbcBJFz5 (ORCPT ); Wed, 10 Feb 2016 00:55:57 -0500 From: Bharat Kumar Gogada To: Paul Burton CC: "bhelgaas@google.com" , Michal Simek , "lorenzo.pieralisi@arm.com" , "yinghai@kernel.org" , "wangyijing@huawei.com" , "robh@kernel.org" , "russell.joyce@york.ac.uk" , Soren Brinkmann , "jiang.liu@linux.intel.com" , "arnd@arndb.de" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Ravikiran Gummaluri Subject: RE: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Wed, 10 Feb 2016 05:55:51 +0000 Message-ID: <8520D5D51A55D047800579B09414719825881780@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1455014518-8708-1-git-send-email-bharatku@xilinx.com> <1455014518-8708-4-git-send-email-bharatku@xilinx.com> <20160209161134.GA24244@NP-P-BURTON> In-Reply-To: <20160209161134.GA24244@NP-P-BURTON> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org List-ID: PiBPbiBUdWUsIEZlYiAwOSwgMjAxNiBhdCAwNDoxMTo1NlBNICswNTMwLCBCaGFyYXQgS3VtYXIg R29nYWRhIHdyb3RlOg0KPiA+IE1vZGlmeWluZyBYaWxpbnggQVhJIFBDSWUgSG9zdCBCcmlkZ2Ug U29mdCBJUCBkcml2ZXIgdG8gd29yayBvbiBib3RoDQo+ID4gWnlucSBhbmQgTWljcm9ibGF6ZSBB cmNoaXRlY3R1cmVzLg0KPiA+IFdpdGggdGhlc2UgbW9kaWZpY2F0aW9ucyBkcml2ZXJzL3BjaS9o b3N0L3BjaWUteGlsaW54LmMsIHdpbGwgd29yayBvbg0KPiA+IGJvdGggWnlucSBhbmQgTWljcm9i bGF6ZSBBcmNoaXRlY3R1cmVzLg0KPiA+DQo+ID4gU2lnbmVkLW9mZi1ieTogQmhhcmF0IEt1bWFy IEdvZ2FkYSA8YmhhcmF0a3VAeGlsaW54LmNvbT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBSYXZpIEtp cmFuIEd1bW1hbHVyaSA8cmd1bW1hbEB4aWxpbnguY29tPg0KPiA+IC0tLQ0KPiA+IENoYW5nZXM6 DQo+ID4gUmVtb3ZlZCB1bm5lY2Nlc3NhcnkgYXJjaGl0ZWN0dXJlIGRlcGVuZGVudCBudW1iZXIg b2YgTVNJJ3MuDQo+ID4gQWRkZWQgI2lmZGVmIHRvIHBjaV9maXh1cF9pcnFzIHdoaWNoIGlzIEFS TSBzcGVjaWZpYyBBUEkuDQo+IA0KPiBIaSBCaGFyYXQsDQo+IA0KPiBXaHkgZG8geW91IHNheSBw Y2lfZml4dXBfaXJxcyBpcyBBUk0tc3BlY2lmaWM/IEl0J3MgZGVjbGFyZWQgaW4NCj4gaW5jbHVk ZS9saW51eC9wY2kuaCwgZGVmaW5lZCBpbiBkcml2ZXJzL3BjaS9zZXR1cC1pcnEuYyAmIHVzZWQg YnkgbXVsdGlwbGUNCj4gYXJjaGl0ZWN0dXJlcyAoYWxwaGEsIGFybSwgbTY4aywgbWlwcywgc2gs IHNwYXJjLCB0aWxlLA0KPiB1bmljb3JlMzIgZnJvbSBhIHF1aWNrIGdyZXApLg0KPiANCj4gV2ls bCB5b3Ugbm90IGJyZWFrIElOVFgtc3R5bGUgaW50ZXJydXB0cyBieSByZW1vdmluZyB0aGlzPw0K PiANCkkgbWVhbnQgdG8gc2F5IEFSTSBzcGVjaWZpYyB3LnIudCBNaWNyb2JsYXplIGFyY2hpdGVj dHVyZSwgd2hpY2ggaXMgd2hhdCB0aGlzIHBhdGNoIHNlcmllcyBhcmUgZm9yLiBUaGlzIGhhcyBi ZWVuIGFscmVhZHkgZGlzY3Vzc2VkIGluIG15IHByZXZpb3VzIHBhdGNoIGJ5ICBBcm5kIEJlcmdt YW5uIGFuZCBMb3JlbnpvIFBpZXJhbGlzaSAuIChodHRwczovL2xrbWwub3JnL2xrbWwvMjAxNi8x LzEyLzcwNykNCg0KQmhhcmF0DQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: bharat.kumar.gogada@xilinx.com (Bharat Kumar Gogada) Date: Wed, 10 Feb 2016 05:55:51 +0000 Subject: [PATCH V3 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze In-Reply-To: <20160209161134.GA24244@NP-P-BURTON> References: <1455014518-8708-1-git-send-email-bharatku@xilinx.com> <1455014518-8708-4-git-send-email-bharatku@xilinx.com> <20160209161134.GA24244@NP-P-BURTON> Message-ID: <8520D5D51A55D047800579B09414719825881780@XAP-PVEXMBX01.xlnx.xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > On Tue, Feb 09, 2016 at 04:11:56PM +0530, Bharat Kumar Gogada wrote: > > Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both > > Zynq and Microblaze Architectures. > > With these modifications drivers/pci/host/pcie-xilinx.c, will work on > > both Zynq and Microblaze Architectures. > > > > Signed-off-by: Bharat Kumar Gogada > > Signed-off-by: Ravi Kiran Gummaluri > > --- > > Changes: > > Removed unneccessary architecture dependent number of MSI's. > > Added #ifdef to pci_fixup_irqs which is ARM specific API. > > Hi Bharat, > > Why do you say pci_fixup_irqs is ARM-specific? It's declared in > include/linux/pci.h, defined in drivers/pci/setup-irq.c & used by multiple > architectures (alpha, arm, m68k, mips, sh, sparc, tile, > unicore32 from a quick grep). > > Will you not break INTX-style interrupts by removing this? > I meant to say ARM specific w.r.t Microblaze architecture, which is what this patch series are for. This has been already discussed in my previous patch by Arnd Bergmann and Lorenzo Pieralisi . (https://lkml.org/lkml/2016/1/12/707) Bharat