From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uwm1E-0005B3-NY for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Uwm1D-0002i5-MX for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:28:44 -0400 Received: from mail-pb0-f44.google.com ([209.85.160.44]:61515) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uwm1D-0002hz-Fu for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:28:43 -0400 Received: by mail-pb0-f44.google.com with SMTP id uo1so6272874pbc.17 for ; Tue, 09 Jul 2013 21:28:42 -0700 (PDT) Sender: Peter Crosthwaite From: peter.crosthwaite@xilinx.com Date: Wed, 10 Jul 2013 14:23:38 +1000 Message-Id: <8549a20530b9331af1c3d725f4cb9a3e4fe3a9b2.1373429432.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: qemu-devel@nongnu.org From: Nathan Rossi Added Vector Base Address remapping on ARM v7. Signed-off-by: Nathan Rossi Signed-off-by: Peter Crosthwaite --- changed since v1: Removed obsolete VMSD logic (rebase) Forced lower 5 bits of VBAR ro 0 (PMM review) Simplified if-else logic to not worry about pre-v7 (PMM review) target-arm/cpu.h | 1 + target-arm/helper.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index abcc0b4..f27ccd5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -138,6 +138,7 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ + uint32_t c12_vbar; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ uint32_t c13_tls1; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index f8b9ef4..4e88754 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -520,6 +520,14 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= (1 << 31); + env->cp15.c12_vbar = value & ~0x1Ful; + return 0; +} + static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -605,6 +613,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenclr_write, }, + { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), + .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .resetvalue = 0, }, @@ -2134,7 +2146,17 @@ void arm_cpu_do_interrupt(CPUState *cs) } /* High vectors. */ if (env->cp15.c1_sys & (1 << 13)) { + /* when enabled, base address cannot be remapped. */ addr += 0xffff0000; + } else { + /* ARM v7 architectures provide a vector base address register to remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and has a secure + * and un-secure copy. Since the cpu is always in a un-secure operation + * and is never in monitor mode this feature is always active. + * Note: only bits 31:5 are valid. + */ + addr += env->cp15.c12_vbar; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); -- 1.8.3.rc1.44.gb387c77.dirty