On 04/30/2018 07:15 PM, speck for Konrad Rzeszutek Wilk wrote:
> On Mon, Apr 30, 2018 at 06:25:52PM -0700, speck for Tim Chen wrote:
>> On 04/30/2018 08:04 AM, speck for Thomas Gleixner wrote:
>>
>>>
>>> void x86_set_spec_ctrl(u64 val)
>>> {
>>> -	if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS))
>>> +	if (val & x86_spec_ctrl_mask)
>>> 		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
>>> 	else
>>> 		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
>>> @@ -459,6 +465,7 @@ static enum ssb_mitigation_cmd __init __
>>> 		switch (boot_cpu_data.x86_vendor) {
>>> 		case X86_VENDOR_INTEL:
>>> 			x86_spec_ctrl_base |= SPEC_CTRL_RDS;
>>> +			x86_spec_ctrl_mask &= ~(SPEC_CTRL_RDS);
>>> 			x86_set_spec_ctrl(SPEC_CTRL_RDS);
>>
>> We only have cpu 0's RDS set when we ask for SSB to be turned off for whole system
>> in current v8 patchset.
>>
>> I noticed that the x86_set_spec_ctrl call in
>> init_intel got dropped in current patchset.  It was in Konrad's original patchset.
> 
> Hm, does  see x86_setup_ap_spec_ctrl not get called from identify_secondary_cpu?

It got called but

void x86_setup_ap_spec_ctrl(void)
{
        if (boot_cpu_has(X86_FEATURE_IBRS))
                x86_set_spec_ctrl(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);

        if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
                x86_amd_rds_enable();
}

So I guess only amd cpu gets the love :)

Tim


> 
> 
> Granted I recall seeing a patch from Thomas on LKML about a regression
> of X86_FEATURE_IBRS being cleared on AP processors - perhaps that is
> exatly what you are hitting?
> 
> What happens if you change the check from X86_FEATURE_IBRS to
> X86_FEATURE_SPEC_STORE_BYPASS_DISABLE in x86_setup_ap_spec_ctrl?
>