From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B326BC282C8 for ; Mon, 28 Jan 2019 10:37:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C540214DA for ; Mon, 28 Jan 2019 10:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726713AbfA1KhV (ORCPT ); Mon, 28 Jan 2019 05:37:21 -0500 Received: from foss.arm.com ([217.140.101.70]:42958 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726415AbfA1KhV (ORCPT ); Mon, 28 Jan 2019 05:37:21 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F1C2AEBD; Mon, 28 Jan 2019 02:37:20 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7654E3F589; Mon, 28 Jan 2019 02:37:18 -0800 (PST) Date: Mon, 28 Jan 2019 10:37:18 +0000 Message-ID: <867eepvzj5.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Cc: , , , , , , , , Subject: Re: [PATCH v9 13/26] arm64: daifflags: Include PMR in daifflags restore operations In-Reply-To: <1548084825-8803-14-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-14-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Jan 2019 15:33:32 +0000, Julien Thierry wrote: > > The addition of PMR should not bypass the semantics of daifflags. > > When DA_F are set, I bit is also set as no interrupts (even of higher > priority) is allowed. > > When DA_F are cleared, I bit is cleared and interrupt enabling/disabling > goes through ICC_PMR_EL1. > > Signed-off-by: Julien Thierry > Reviewed-by: Catalin Marinas > Cc: Catalin Marinas > Cc: Will Deacon > Cc: James Morse > --- > arch/arm64/include/asm/daifflags.h | 31 +++++++++++++++++++++++++++---- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h > index 546bc39..1fd390e 100644 > --- a/arch/arm64/include/asm/daifflags.h > +++ b/arch/arm64/include/asm/daifflags.h > @@ -18,6 +18,8 @@ > > #include > > +#include > + > #define DAIF_PROCCTX 0 > #define DAIF_PROCCTX_NOIRQ PSR_I_BIT > > @@ -36,7 +38,13 @@ static inline unsigned long local_daif_save(void) > { > unsigned long flags; > > - flags = arch_local_save_flags(); > + flags = read_sysreg(daif); > + > + if (system_uses_irq_prio_masking()) { > + /* If IRQs are masked with PMR, reflect it in the flags */ > + if (read_sysreg_s(SYS_ICC_PMR_EL1) <= GIC_PRIO_IRQOFF) > + flags |= PSR_I_BIT; > + } > > local_daif_mask(); > > @@ -45,12 +53,27 @@ static inline unsigned long local_daif_save(void) > > static inline void local_daif_restore(unsigned long flags) > { > - if (!arch_irqs_disabled_flags(flags)) > + bool irq_disabled = flags & PSR_I_BIT; > + > + if (!irq_disabled) { > trace_hardirqs_on(); > > - arch_local_irq_restore(flags); > + if (system_uses_irq_prio_masking()) > + arch_local_irq_enable(); > + } else if (!(flags & PSR_A_BIT)) { > + /* > + * If interrupts are disabled but we can take > + * asynchronous errors, we can take NMIs > + */ > + if (system_uses_irq_prio_masking()) { > + flags &= ~PSR_I_BIT; > + arch_local_irq_disable(); > + } > + } > + > + write_sysreg(flags, daif); After much head scratching, I finally came to the conclusion that the above is safe, as a write to PSTATE is guaranteed not to be visible to instructions before it in program order (and the write to PMR is itself self-synchronising). I guess that a reference to the ARM ARM is in order here (no pun intended...). > > - if (arch_irqs_disabled_flags(flags)) > + if (irq_disabled) > trace_hardirqs_off(); > } > > -- > 1.9.1 > With the above, Reviewed-by: Marc Zyngier M. -- Jazz is not dead, it just smell funny. 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1go4IN-0001uD-1x; Mon, 28 Jan 2019 10:37:39 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1go4I5-0001iO-O0 for linux-arm-kernel@lists.infradead.org; Mon, 28 Jan 2019 10:37:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F1C2AEBD; Mon, 28 Jan 2019 02:37:20 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7654E3F589; Mon, 28 Jan 2019 02:37:18 -0800 (PST) Date: Mon, 28 Jan 2019 10:37:18 +0000 Message-ID: <867eepvzj5.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Subject: Re: [PATCH v9 13/26] arm64: daifflags: Include PMR in daifflags restore operations In-Reply-To: <1548084825-8803-14-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-14-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190128_023722_025496_E53FBA6D X-CRM114-Status: GOOD ( 23.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 21 Jan 2019 15:33:32 +0000, Julien Thierry wrote: > > The addition of PMR should not bypass the semantics of daifflags. > > When DA_F are set, I bit is also set as no interrupts (even of higher > priority) is allowed. > > When DA_F are cleared, I bit is cleared and interrupt enabling/disabling > goes through ICC_PMR_EL1. > > Signed-off-by: Julien Thierry > Reviewed-by: Catalin Marinas > Cc: Catalin Marinas > Cc: Will Deacon > Cc: James Morse > --- > arch/arm64/include/asm/daifflags.h | 31 +++++++++++++++++++++++++++---- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h > index 546bc39..1fd390e 100644 > --- a/arch/arm64/include/asm/daifflags.h > +++ b/arch/arm64/include/asm/daifflags.h > @@ -18,6 +18,8 @@ > > #include > > +#include > + > #define DAIF_PROCCTX 0 > #define DAIF_PROCCTX_NOIRQ PSR_I_BIT > > @@ -36,7 +38,13 @@ static inline unsigned long local_daif_save(void) > { > unsigned long flags; > > - flags = arch_local_save_flags(); > + flags = read_sysreg(daif); > + > + if (system_uses_irq_prio_masking()) { > + /* If IRQs are masked with PMR, reflect it in the flags */ > + if (read_sysreg_s(SYS_ICC_PMR_EL1) <= GIC_PRIO_IRQOFF) > + flags |= PSR_I_BIT; > + } > > local_daif_mask(); > > @@ -45,12 +53,27 @@ static inline unsigned long local_daif_save(void) > > static inline void local_daif_restore(unsigned long flags) > { > - if (!arch_irqs_disabled_flags(flags)) > + bool irq_disabled = flags & PSR_I_BIT; > + > + if (!irq_disabled) { > trace_hardirqs_on(); > > - arch_local_irq_restore(flags); > + if (system_uses_irq_prio_masking()) > + arch_local_irq_enable(); > + } else if (!(flags & PSR_A_BIT)) { > + /* > + * If interrupts are disabled but we can take > + * asynchronous errors, we can take NMIs > + */ > + if (system_uses_irq_prio_masking()) { > + flags &= ~PSR_I_BIT; > + arch_local_irq_disable(); > + } > + } > + > + write_sysreg(flags, daif); After much head scratching, I finally came to the conclusion that the above is safe, as a write to PSTATE is guaranteed not to be visible to instructions before it in program order (and the write to PMR is itself self-synchronising). I guess that a reference to the ARM ARM is in order here (no pun intended...). > > - if (arch_irqs_disabled_flags(flags)) > + if (irq_disabled) > trace_hardirqs_off(); > } > > -- > 1.9.1 > With the above, Reviewed-by: Marc Zyngier M. -- Jazz is not dead, it just smell funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel