Here are a few bug fixes for drm/i915. This fixes switching from
interlaced to non-interlaced mode at boot time, as well as a bunch of
regressions caused by bad DP bandwidth computations.

The following changes since commit acb42a3b611d7ad4cb173c3b37674b549df2ffeb:

  Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2012-01-27 07:56:25 -0800)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux drm-intel-fixes

for you to fetch changes up to 617cf884810b44384fe8e9431e9babeb80a2ff37:

  drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2) (2012-02-08 13:54:18 -0800)

----------------------------------------------------------------
Chris Wilson (1):
      drm/i915:: Disable FBC on SandyBridge

Daniel Vetter (2):
      drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
      drm/i915: no lvds quirk for AOpen MP45

Keith Packard (2):
      drm/i915: Force explicit bpp selection for intel_dp_link_required
      drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2)

 drivers/gpu/drm/i915/intel_display.c |    8 +++++---
 drivers/gpu/drm/i915/intel_dp.c      |   20 +++++---------------
 drivers/gpu/drm/i915/intel_lvds.c    |    8 ++++++++
 3 files changed, 18 insertions(+), 18 deletions(-)

-- 
keith.packard@intel.com