From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6604C4361B for ; Mon, 14 Dec 2020 01:36:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 817662388A for ; Mon, 14 Dec 2020 01:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437750AbgLNBgd (ORCPT ); Sun, 13 Dec 2020 20:36:33 -0500 Received: from foss.arm.com ([217.140.110.172]:43084 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725905AbgLNBgc (ORCPT ); Sun, 13 Dec 2020 20:36:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BB201FB; Sun, 13 Dec 2020 17:35:46 -0800 (PST) Received: from [192.168.2.22] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60E7F3F66E; Sun, 13 Dec 2020 17:35:44 -0800 (PST) Subject: Re: [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling To: Icenowy Zheng , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Icenowy Zheng , Linus Walleij , Rob Herring , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Shuosheng Huang , Yangtao Li , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Kishon Vijay Abraham I , Vinod Koul References: <20201211011934.6171-1-andre.przywara@arm.com> <20201211011934.6171-15-andre.przywara@arm.com> <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io> From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Autocrypt: addr=andre.przywara@arm.com; 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Message-ID: <86fd61f1-9bdd-5004-758b-8e21134fadd2@arm.com> Date: Mon, 14 Dec 2020 01:35:37 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/12/2020 18:24, Icenowy Zheng wrote: > 在 2020-12-11星期五的 01:19 +0000，Andre Przywara写道： >> Newer SoCs (A100, H616) need to clear a different bit in our >> "unknown" >> PMU PHY register. > > It looks like that the unknown PHY register is PHYCTL register for each > individual PHY, and the bit that is cleared is > called SUNXI_HCI_PHY_CTRL_SIDDQ in the BSP (similar to > the USBC_PHY_CTL_SIDDQ we cleared for main PHYCTL). Oh, right, somehow I failed to find this in the BSP, I guess I got confused over that similar symbol. I will put proper names to it. Thanks! Andre >> >> Generalise the existing code by allowing configs to specify a bitmask >> of bits to clear. >> >> Signed-off-by: Andre Przywara >> --- >> drivers/phy/allwinner/phy-sun4i-usb.c | 28 +++++++++++------------ >> ---- >> 1 file changed, 11 insertions(+), 17 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c >> b/drivers/phy/allwinner/phy-sun4i-usb.c >> index 651d5e2a25ce..4ba0699e0bb4 100644 >> --- a/drivers/phy/allwinner/phy-sun4i-usb.c >> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c >> @@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg { >> int hsic_index; >> enum sun4i_usb_phy_type type; >> u32 disc_thresh; >> + u32 pmu_unk1_clrbits; >> u8 phyctl_offset; >> bool dedicated_clocks; >> - bool enable_pmu_unk1; >> bool phy0_dual_route; >> int missing_phys; >> }; >> @@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) >> return ret; >> } >> >> + if (phy->pmu && data->cfg->pmu_unk1_clrbits) { >> + val = readl(phy->pmu + REG_PMU_UNK1); >> + val &= ~data->cfg->pmu_unk1_clrbits; >> + writel(val, phy->pmu + REG_PMU_UNK1); >> + } >> + >> if (data->cfg->type == sun8i_a83t_phy || >> data->cfg->type == sun50i_h6_phy) { >> if (phy->index == 0) { >> @@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) >> writel(val, data->base + data->cfg- >>> phyctl_offset); >> } >> } else { >> - if (phy->pmu && data->cfg->enable_pmu_unk1) { >> - val = readl(phy->pmu + REG_PMU_UNK1); >> - writel(val & ~2, phy->pmu + REG_PMU_UNK1); >> - } >> - >> /* Enable USB 45 Ohm resistor calibration */ >> if (phy->index == 0) >> sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, >> 0x01, 1); >> @@ -867,7 +868,6 @@ static const struct sun4i_usb_phy_cfg >> sun4i_a10_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A10, >> .dedicated_clocks = false, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { >> @@ -876,7 +876,6 @@ static const struct sun4i_usb_phy_cfg >> sun5i_a13_cfg = { >> .disc_thresh = 2, >> .phyctl_offset = REG_PHYCTL_A10, >> .dedicated_clocks = false, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { >> @@ -885,7 +884,6 @@ static const struct sun4i_usb_phy_cfg >> sun6i_a31_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A10, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { >> @@ -894,7 +892,6 @@ static const struct sun4i_usb_phy_cfg >> sun7i_a20_cfg = { >> .disc_thresh = 2, >> .phyctl_offset = REG_PHYCTL_A10, >> .dedicated_clocks = false, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { >> @@ -903,7 +900,6 @@ static const struct sun4i_usb_phy_cfg >> sun8i_a23_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A10, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { >> @@ -912,7 +908,6 @@ static const struct sun4i_usb_phy_cfg >> sun8i_a33_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = false, >> }; >> >> static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { >> @@ -929,7 +924,7 @@ static const struct sun4i_usb_phy_cfg >> sun8i_h3_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> + .pmu_unk1_clrbits = BIT(1), >> .phy0_dual_route = true, >> }; >> >> @@ -939,7 +934,7 @@ static const struct sun4i_usb_phy_cfg >> sun8i_r40_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> + .pmu_unk1_clrbits = BIT(1), >> .phy0_dual_route = true, >> }; >> >> @@ -949,7 +944,7 @@ static const struct sun4i_usb_phy_cfg >> sun8i_v3s_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> + .pmu_unk1_clrbits = BIT(1), >> .phy0_dual_route = true, >> }; >> >> @@ -959,7 +954,7 @@ static const struct sun4i_usb_phy_cfg >> sun50i_a64_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> + .pmu_unk1_clrbits = BIT(1), >> .phy0_dual_route = true, >> }; >> >> @@ -969,7 +964,6 @@ static const struct sun4i_usb_phy_cfg >> sun50i_h6_cfg = { >> .disc_thresh = 3, >> .phyctl_offset = REG_PHYCTL_A33, >> .dedicated_clocks = true, >> - .enable_pmu_unk1 = true, >> .phy0_dual_route = true, >> .missing_phys = BIT(1) | BIT(2), >> }; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1202EC4361B for ; Mon, 14 Dec 2020 01:37:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A49823787 for ; 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Message-ID: <86fd61f1-9bdd-5004-758b-8e21134fadd2@arm.com> Date: Mon, 14 Dec 2020 01:35:37 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201213_203551_395344_97F9C7B0 X-CRM114-Status: GOOD ( 20.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Vinod Koul , Yangtao Li , Linus Walleij , linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , linux-sunxi@googlegroups.com, =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Icenowy Zheng , Shuosheng Huang , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: 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