From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932883AbeCJMU0 (ORCPT ); Sat, 10 Mar 2018 07:20:26 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:35392 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932528AbeCJMUZ (ORCPT ); Sat, 10 Mar 2018 07:20:25 -0500 Date: Sat, 10 Mar 2018 12:20:19 +0000 Message-ID: <86k1ukazr0.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Christoffer Dall Cc: Shunyong Yang , ard.biesheuvel@linaro.org, will.deacon@arm.com, eric.auger@redhat.com, david.daney@cavium.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, Joey Zheng Subject: Re: [RFC PATCH] KVM: arm/arm64: vgic: change condition for level interrupt resampling In-Reply-To: <20180309213612.GD1917@lvm> References: <1520492490-7943-1-git-send-email-shunyong.yang@hxt-semitech.com> <9ad47673-068e-f732-d2ca-9c76a8fbdfbc@arm.com> <0a15633d-8944-cb9b-3e6b-b08ee5ec42b9@arm.com> <20180308161900.GC1917@lvm> <86r2oubho3.wl-marc.zyngier@arm.com> <20180309213612.GD1917@lvm> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 09 Mar 2018 21:36:12 +0000, Christoffer Dall wrote: > > On Thu, Mar 08, 2018 at 05:28:44PM +0000, Marc Zyngier wrote: > > I'd be more confident if we did forbid P+A for such interrupts > > altogether, as they really feel like another kind of HW interrupt. > > How about a slightly bigger hammer: Can we avoid doing P+A for level > interrupts completely? I don't think that really makes much sense, and > I think we simply everything if we just come back out and resample the > line. For an edge, something like a network card, there's a potential > performance win to appending a new pending state, but I doubt that this > is the case for level interrupts. I started implementing the same thing yesterday. Somehow, it feels slightly better to have the same flow for all level interrupts, including the timer, and we only use the MI on EOI as a way to trigger the next state of injection. Still testing, but looking good so far. I'm still puzzled that we have this level-but-not-quite behaviour for VFIO interrupts. At some point, it is going to bite us badly. M. -- Jazz is not dead, it just smell funny. From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Sat, 10 Mar 2018 12:20:19 +0000 Subject: [RFC PATCH] KVM: arm/arm64: vgic: change condition for level interrupt resampling In-Reply-To: <20180309213612.GD1917@lvm> References: <1520492490-7943-1-git-send-email-shunyong.yang@hxt-semitech.com> <9ad47673-068e-f732-d2ca-9c76a8fbdfbc@arm.com> <0a15633d-8944-cb9b-3e6b-b08ee5ec42b9@arm.com> <20180308161900.GC1917@lvm> <86r2oubho3.wl-marc.zyngier@arm.com> <20180309213612.GD1917@lvm> Message-ID: <86k1ukazr0.wl-marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 09 Mar 2018 21:36:12 +0000, Christoffer Dall wrote: > > On Thu, Mar 08, 2018 at 05:28:44PM +0000, Marc Zyngier wrote: > > I'd be more confident if we did forbid P+A for such interrupts > > altogether, as they really feel like another kind of HW interrupt. > > How about a slightly bigger hammer: Can we avoid doing P+A for level > interrupts completely? I don't think that really makes much sense, and > I think we simply everything if we just come back out and resample the > line. For an edge, something like a network card, there's a potential > performance win to appending a new pending state, but I doubt that this > is the case for level interrupts. I started implementing the same thing yesterday. Somehow, it feels slightly better to have the same flow for all level interrupts, including the timer, and we only use the MI on EOI as a way to trigger the next state of injection. Still testing, but looking good so far. I'm still puzzled that we have this level-but-not-quite behaviour for VFIO interrupts. At some point, it is going to bite us badly. M. -- Jazz is not dead, it just smell funny.