From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55DFCC31E4A for ; Thu, 13 Jun 2019 15:48:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3916420851 for ; Thu, 13 Jun 2019 15:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389522AbfFMPsE (ORCPT ); Thu, 13 Jun 2019 11:48:04 -0400 Received: from foss.arm.com ([217.140.110.172]:36970 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731741AbfFMJXK (ORCPT ); Thu, 13 Jun 2019 05:23:10 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22F64367; Thu, 13 Jun 2019 02:23:10 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 248A83F694; Thu, 13 Jun 2019 02:23:07 -0700 (PDT) Date: Thu, 13 Jun 2019 10:22:33 +0100 Message-ID: <86muilc012.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Benjamin Herrenschmidt Cc: Thomas Petazzoni , Gregory CLEMENT , , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH+DISCUSSION] irqchip: armada-370-xp: Remove redundant ops assignment In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ben, On Wed, 12 Jun 2019 06:16:05 +0100, Benjamin Herrenschmidt wrote: > > pci_msi_create_irq_domain -> pci_msi_domain_update_chip_ops will > set those two already since the driver sets MSI_FLAG_USE_DEF_CHIP_OPS > > Signed-off-by: Benjamin Herrenschmidt > --- > > [UNTESTED] > > Just something I noticed while browsing through those drivers in > search of ways to factor some of the code. > > That leads to a question here: > > Some MSI drivers such as this one (or any using the defaults mask/unmask > provided by drivers/pci/msi.c) only call the PCI MSI mask/unmask functions. > > Some other drivers call those PCI function but *also* call the parent > mask/unmask (giv-v2m for example) which generally is the inner domain > which just itself forwards to its own parent. > > Is there any preference for doing it one way or the other ? I can see > that in cases where the device doesn't support MSI masking, calling the > parent could be useful but we don't know that at the moment in the > corresponding code. > > It feels like something we should consolidate (and remove code from > drivers). For example, the defaults in drivers/pci/msi.c could always > call the parent if it exists and has a mask/unmask callback. > > Opinions ? I'm happy to produce patches once we agree... > > diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c > index c9bdc5221b82..911230f28e2d 100644 > --- a/drivers/irqchip/irq-armada-370-xp.c > +++ b/drivers/irqchip/irq-armada-370-xp.c > @@ -197,8 +197,6 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) > > static struct irq_chip armada_370_xp_msi_irq_chip = { > .name = "MPIC MSI", > - .irq_mask = pci_msi_mask_irq, > - .irq_unmask = pci_msi_unmask_irq, > }; > > static struct msi_domain_info armada_370_xp_msi_domain_info = { > It looks to me that masking at the PCI level is rather superfluous as long as the MSI controller HW has the capability to mask the interrupt on a per MSI basis. After all, most non MSI-X endpoint lack support for masking of individual vectors, so I think that we should just mask things at the irqchip level. This is also consistent with what you'd have to do for non-PCI MSI, where nothing standardises the MSI masking. I think this is in effect a split in responsibilities: - the end-point driver should (directly or indirectly) control the interrupt generation at the end-point level, - the MSI controller driver should control the signalling of the MSI to the CPU. The only case where we should rely on masking interrupts at the end-point level is when the MSI controller doesn't provide a method to do so (hopefully a rare exception). To take the example of the gicv2m driver that you mention above, I'd suggest the following: diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 3c77ab676e54..2ce801207acd 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -72,22 +72,10 @@ struct v2m_data { u32 flags; /* v2m flags for specific implementation */ }; -static void gicv2m_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void gicv2m_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} - static struct irq_chip gicv2m_msi_irq_chip = { .name = "MSI", - .irq_mask = gicv2m_mask_msi_irq, - .irq_unmask = gicv2m_unmask_msi_irq, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, .irq_eoi = irq_chip_eoi_parent, .irq_write_msi_msg = pci_msi_domain_write_msg, }; The same should be applied to a number of drivers in the tree, which seem to have cargo-culted the wrong idiom (and I take responsibility for that). Thanks, M. -- Jazz is not dead, it just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B159C31E45 for ; Thu, 13 Jun 2019 09:23:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32BA62147A for ; Thu, 13 Jun 2019 09:23:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hNQIMZHZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32BA62147A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hPCM0IORT3o+r/gixG34f9nUUyiBO79JftMlcrbysqU=; b=hNQIMZHZL9l8cx rxkFuAD0CyeMVvQDgqtfrn/3AZgfVsWeneMdoJvZFpXbIy3nF27l7ZukW306P0SBJRqCsz2KO8y6E 5lidkCMNj2UMmduj8gXS/5i1XV4hGSFDA8Qu/f2HdyMit/eGp4zAvj6AC2NCF3KYF15Us7eUT5zHT g9tDUfCg+axrsGz+IIXJmCUJE+1s3GBgaEcMGq20iwH7qe9cHAO0xwOvV97MLz4FHUzQGLitaFY5P ICkYQTajQPTdBvLdROSQLTudiBUHUe8MlkQ4xbyeyAZHNdeiTuMiG5Si9NbgF8xkkXa1L/j4yQZVy ePJrYpV0wbH0PPl3NnTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hbLwx-0001PN-EF; Thu, 13 Jun 2019 09:23:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hbLws-0001Nu-U7 for linux-arm-kernel@lists.infradead.org; Thu, 13 Jun 2019 09:23:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22F64367; Thu, 13 Jun 2019 02:23:10 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 248A83F694; Thu, 13 Jun 2019 02:23:07 -0700 (PDT) Date: Thu, 13 Jun 2019 10:22:33 +0100 Message-ID: <86muilc012.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Benjamin Herrenschmidt Subject: Re: [PATCH+DISCUSSION] irqchip: armada-370-xp: Remove redundant ops assignment In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190613_022311_057385_A8B66487 X-CRM114-Status: GOOD ( 29.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Gregory CLEMENT , "linux-kernel@vger.kernel.org" , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Ben, On Wed, 12 Jun 2019 06:16:05 +0100, Benjamin Herrenschmidt wrote: > > pci_msi_create_irq_domain -> pci_msi_domain_update_chip_ops will > set those two already since the driver sets MSI_FLAG_USE_DEF_CHIP_OPS > > Signed-off-by: Benjamin Herrenschmidt > --- > > [UNTESTED] > > Just something I noticed while browsing through those drivers in > search of ways to factor some of the code. > > That leads to a question here: > > Some MSI drivers such as this one (or any using the defaults mask/unmask > provided by drivers/pci/msi.c) only call the PCI MSI mask/unmask functions. > > Some other drivers call those PCI function but *also* call the parent > mask/unmask (giv-v2m for example) which generally is the inner domain > which just itself forwards to its own parent. > > Is there any preference for doing it one way or the other ? I can see > that in cases where the device doesn't support MSI masking, calling the > parent could be useful but we don't know that at the moment in the > corresponding code. > > It feels like something we should consolidate (and remove code from > drivers). For example, the defaults in drivers/pci/msi.c could always > call the parent if it exists and has a mask/unmask callback. > > Opinions ? I'm happy to produce patches once we agree... > > diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c > index c9bdc5221b82..911230f28e2d 100644 > --- a/drivers/irqchip/irq-armada-370-xp.c > +++ b/drivers/irqchip/irq-armada-370-xp.c > @@ -197,8 +197,6 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) > > static struct irq_chip armada_370_xp_msi_irq_chip = { > .name = "MPIC MSI", > - .irq_mask = pci_msi_mask_irq, > - .irq_unmask = pci_msi_unmask_irq, > }; > > static struct msi_domain_info armada_370_xp_msi_domain_info = { > It looks to me that masking at the PCI level is rather superfluous as long as the MSI controller HW has the capability to mask the interrupt on a per MSI basis. After all, most non MSI-X endpoint lack support for masking of individual vectors, so I think that we should just mask things at the irqchip level. This is also consistent with what you'd have to do for non-PCI MSI, where nothing standardises the MSI masking. I think this is in effect a split in responsibilities: - the end-point driver should (directly or indirectly) control the interrupt generation at the end-point level, - the MSI controller driver should control the signalling of the MSI to the CPU. The only case where we should rely on masking interrupts at the end-point level is when the MSI controller doesn't provide a method to do so (hopefully a rare exception). To take the example of the gicv2m driver that you mention above, I'd suggest the following: diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 3c77ab676e54..2ce801207acd 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -72,22 +72,10 @@ struct v2m_data { u32 flags; /* v2m flags for specific implementation */ }; -static void gicv2m_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void gicv2m_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} - static struct irq_chip gicv2m_msi_irq_chip = { .name = "MSI", - .irq_mask = gicv2m_mask_msi_irq, - .irq_unmask = gicv2m_unmask_msi_irq, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, .irq_eoi = irq_chip_eoi_parent, .irq_write_msi_msg = pci_msi_domain_write_msg, }; The same should be applied to a number of drivers in the tree, which seem to have cargo-culted the wrong idiom (and I take responsibility for that). Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel