From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5873AC433EF for ; Thu, 7 Jul 2022 12:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235268AbiGGMox (ORCPT ); Thu, 7 Jul 2022 08:44:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235158AbiGGMou (ORCPT ); Thu, 7 Jul 2022 08:44:50 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DF3B1C929 for ; Thu, 7 Jul 2022 05:44:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 557ADB8215E for ; Thu, 7 Jul 2022 12:44:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BFE3C3411E; Thu, 7 Jul 2022 12:44:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657197887; bh=yHBsLHVANFwi8/WfCTCmLqQ6f66Bg9tjKUuoySwWfZc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=o7+2CWuwp3FMZEwmtj5rd2lafppXOC9XZeNWzg0M10EUorhcnls+hPNmt/D7gDcgy EgDo8U4Kr2Z2kQLHvhHZY1d3+1H6YQoCnZRpcu6jmDvIs/lpxqbCAqpVlN555K85Mx B7O4hTJbGREi498i3mCi15Yp9lss+40YerEXNyAN3oJXp0cJlhlvMA6ViNQ60L3Uit FeemxleAmyKlW3/EXJHcNrakNd317iVkAFgrxSQ7YBTFAPE+xeYXUN2VIjegEfJN8f RpZ8kn4YSdDokrNzPGfJMqU3BSCCN6EA8ey18qXzHyqFcYH974ISm6JkJoPGSm8uPR 8M+Rd2uKb8xAw== Received: from [185.201.63.253] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o9Qs8-005unC-HI; Thu, 07 Jul 2022 13:44:45 +0100 Date: Thu, 07 Jul 2022 13:44:42 +0100 Message-ID: <871quxm6rp.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V14 13/15] irqchip: Add LoongArch CPU interrupt controller support In-Reply-To: <1656837932-18257-14-git-send-email-lvjianmin@loongson.cn> References: <1656837932-18257-1-git-send-email-lvjianmin@loongson.cn> <1656837932-18257-14-git-send-email-lvjianmin@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.201.63.253 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 03 Jul 2022 09:45:30 +0100, Jianmin Lv wrote: > > From: Huacai Chen > > LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt > controller that described in Section 7.4 of "LoongArch Reference Manual, > Vol 1". For more information please refer Documentation/loongarch/irq- > chip-model.rst. > > LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI > (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be > created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded > bits, so we define get_xxx_irq() for them. I really dislike this practice. Even if these 3 interrupts are well known (their hwirqs are set in stone), you should be able to directly create the interrupt from the rest of the kernel code. All you have to do is to expose the fwnode_handle in the arch code (just like you do for other interrupt controllers), retrieve the domain and perform the mapping. No need for any extra arch-specific API in the irqchip controller. It would also be good to mention that this irqchip driver also probes the all the rest of the interrupt hierarchy. Thanks, M. -- Without deviation from the norm, progress is not possible.