From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2CFAC433ED for ; Thu, 8 Apr 2021 13:06:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BAD8F61177 for ; Thu, 8 Apr 2021 13:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231195AbhDHNGb (ORCPT ); Thu, 8 Apr 2021 09:06:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:60860 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbhDHNGb (ORCPT ); Thu, 8 Apr 2021 09:06:31 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2522C6113B; Thu, 8 Apr 2021 13:06:20 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lUUMU-006JIv-1d; Thu, 08 Apr 2021 14:06:18 +0100 Date: Thu, 08 Apr 2021 14:06:17 +0100 Message-ID: <871rblorhy.wl-maz@kernel.org> From: Marc Zyngier To: Stephan Gerhold Cc: Bjorn Andersson , Andy Gross , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: Re: [PATCH] arm64: dts: qcom: msm8916: Add GICv2 hypervisor registers/interrupt In-Reply-To: <20210407163648.4708-1-stephan@gerhold.net> References: <20210407163648.4708-1-stephan@gerhold.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: stephan@gerhold.net, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Stephan, On Wed, 07 Apr 2021 17:36:48 +0100, Stephan Gerhold wrote: > > The ARM Cortex-A53 CPU cores and QGIC2 interrupt controller > (an implementation of the ARM GIC 2.0 specification) used in MSM8916 > support virtualization, e.g. for KVM on Linux. However, so far it was > not possible to make use of this functionality, because Qualcomm's > proprietary "hyp" firmware blocks the EL2 mode of the CPU and only > allows booting Linux in EL1. > > However, on devices without (firmware) secure boot there is no need > to rely on all of Qualcomm's firmware. The "hyp" firmware on MSM8916 > seems simple enough that it can be replaced with an open-source > alternative created only based on trial and error - with some similar > EL2/EL1 initialization code adapted from Linux and U-Boot. Ay, Quaramba! That's great news! > > qhypstub [1] is such an open-source firmware for MSM8916 that > can be used as drop-in replacement for Qualcomm's "hyp" firmware. > It does not implement any hypervisor functionality. > Instead, it allows booting Linux/KVM (or other hypervisors) in EL2. Do you happen to know if the same method would apply to other SoCs from the same vendor? /me eyes the Lenovo c630 that is getting bored with EL1 only... > > With Linux booting in EL2, KVM seems to be working just fine on MSM8916. > However, so far it is not possible to make use of the virtualization > features in the GICv2. To use KVM's VGICv2 code, the QGIC2 device tree > node needs additional resources (according to binding documentation): > > - The CPU interface region (second reg) must be at least 8 KiB large > to access the GICC_DIR register (mapped at 0x1000 offset) > - Virtual control/CPU interface register base and size > - Hypervisor maintenance interrupt > > Fortunately, the public APQ8016E TRM [2] provides the required information: > > - The CPU interface region (at 0x0B002000) actually has a size of 8 KiB > - Virtual control/CPU interface register is at 0x0B001000/0x0B004000 > - Hypervisor maintenance interrupt is "PPI #0" > Note: This is a bit strange since almost all other ARM SoCs use > GIC_PPI 9 for this. However, I have verified that this is > indeed the interrupt that fires when bits are set in GICH_HCR. Other SoCs have their maintenance interrupt wired to weird and wonderful interrupts. Given QC's lack of appetite for standards, I'm not totally surprised. > > Add the additional resources to the QGIC2 device tree node in msm8916.dtsi. > There is no functional difference when Linux is started in EL1 since the > additional resources are ignored in that case. > > With these changes (and qhypstub), KVM seems to be fully working on > the DragonBoard 410c (apq8016-sbc) and BQ Aquaris X5 (longcheer-l8910). > > [1]: https://github.com/msm8916-mainline/qhypstub > [2]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf > > Signed-off-by: Stephan Gerhold > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 4c155735fbc9..4f06c0a9c425 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -1766,7 +1766,9 @@ intc: interrupt-controller@b000000 { > compatible = "qcom,msm-qgic2"; > interrupt-controller; > #interrupt-cells = <3>; > - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; > + reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, > + <0x0b001000 0x1000>, <0x0b004000 0x2000>; > + interrupts = ; > }; > > apcs: mailbox@b011000 { Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.