From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753283AbdASWWF (ORCPT ); Thu, 19 Jan 2017 17:22:05 -0500 Received: from mail.savoirfairelinux.com ([208.88.110.44]:60870 "EHLO mail.savoirfairelinux.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753217AbdASWWD (ORCPT ); Thu, 19 Jan 2017 17:22:03 -0500 From: Vivien Didelot To: Gregory CLEMENT , Andrew Lunn , Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S. Miller" , Jason Cooper , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Nadav Haklai , Wilson Ding , Kostya Porotchkin , Joe Zhou , Jon Pannell Subject: Re: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports In-Reply-To: <20170119214934.27442-2-gregory.clement@free-electrons.com> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> Date: Thu, 19 Jan 2017 17:13:12 -0500 Message-ID: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Gregory, Gregory CLEMENT writes: > From: Romain Perier > > Some Marvell ethernet switches have internal ethernet transceivers with > hardcoded phy addresses. These addresses can be greater than the number > of ports or its value might be different than the associated port number. > This is for example the case for MV88E6341 that has 6 ports and internal > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. Isn't there an hardware table used to map the PHY addresses on such chip? > This commits fixes the issue by removing the condition in MDIO callbacks. > > Signed-off-by: Romain Perier > Reviewed-by: Andrew Lunn > Signed-off-by: Gregory CLEMENT The patch is anyway still valid: Reviewed-by: Vivien Didelot Thanks, Vivien From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivien Didelot Subject: Re: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports Date: Thu, 19 Jan 2017 17:13:12 -0500 Message-ID: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Thomas Petazzoni , Jason Cooper , Joe Zhou , Jon Pannell , Nadav Haklai , Kostya Porotchkin , Gregory CLEMENT , Wilson Ding , "David S. Miller" , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth To: Gregory CLEMENT , Andrew Lunn , Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Return-path: In-Reply-To: <20170119214934.27442-2-gregory.clement@free-electrons.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: netdev.vger.kernel.org Hi Gregory, Gregory CLEMENT writes: > From: Romain Perier > > Some Marvell ethernet switches have internal ethernet transceivers with > hardcoded phy addresses. These addresses can be greater than the number > of ports or its value might be different than the associated port number. > This is for example the case for MV88E6341 that has 6 ports and internal > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. Isn't there an hardware table used to map the PHY addresses on such chip? > This commits fixes the issue by removing the condition in MDIO callbacks. > > Signed-off-by: Romain Perier > Reviewed-by: Andrew Lunn > Signed-off-by: Gregory CLEMENT The patch is anyway still valid: Reviewed-by: Vivien Didelot Thanks, Vivien From mboxrd@z Thu Jan 1 00:00:00 1970 From: vivien.didelot@savoirfairelinux.com (Vivien Didelot) Date: Thu, 19 Jan 2017 17:13:12 -0500 Subject: [PATCH v5 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports In-Reply-To: <20170119214934.27442-2-gregory.clement@free-electrons.com> References: <20170119214934.27442-1-gregory.clement@free-electrons.com> <20170119214934.27442-2-gregory.clement@free-electrons.com> Message-ID: <871svylmvb.fsf@weeman.i-did-not-set--mail-host-address--so-tickle-me> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Gregory, Gregory CLEMENT writes: > From: Romain Perier > > Some Marvell ethernet switches have internal ethernet transceivers with > hardcoded phy addresses. These addresses can be greater than the number > of ports or its value might be different than the associated port number. > This is for example the case for MV88E6341 that has 6 ports and internal > Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14. Isn't there an hardware table used to map the PHY addresses on such chip? > This commits fixes the issue by removing the condition in MDIO callbacks. > > Signed-off-by: Romain Perier > Reviewed-by: Andrew Lunn > Signed-off-by: Gregory CLEMENT The patch is anyway still valid: Reviewed-by: Vivien Didelot Thanks, Vivien