From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AFB2C433E0 for ; Wed, 24 Feb 2021 17:40:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8CDE64EC4 for ; Wed, 24 Feb 2021 17:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235489AbhBXRkc (ORCPT ); Wed, 24 Feb 2021 12:40:32 -0500 Received: from mail.kernel.org ([198.145.29.99]:52974 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232821AbhBXRkZ (ORCPT ); Wed, 24 Feb 2021 12:40:25 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A785364F14; Wed, 24 Feb 2021 17:39:44 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lEy8U-00FjYK-CF; Wed, 24 Feb 2021 17:39:42 +0000 Date: Wed, 24 Feb 2021 17:39:41 +0000 Message-ID: <8735xl1i1u.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: Yanan Wang , Will Deacon , Catalin Marinas , James Morse , Julien Thierry , Suzuki K Poulose , Gavin Shan , Quentin Perret , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 1/4] KVM: arm64: Move the clean of dcache to the map handler In-Reply-To: <70b2d6c2-709b-d63b-1409-b16dad89b9b6@arm.com> References: <20210208112250.163568-1-wangyanan55@huawei.com> <20210208112250.163568-2-wangyanan55@huawei.com> <70b2d6c2-709b-d63b-1409-b16dad89b9b6@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, wangyanan55@huawei.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, gshan@redhat.com, qperret@google.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 24 Feb 2021 17:21:22 +0000, Alexandru Elisei wrote: > > Hello, > > On 2/8/21 11:22 AM, Yanan Wang wrote: > > We currently uniformly clean dcache in user_mem_abort() before calling the > > fault handlers, if we take a translation fault and the pfn is cacheable. > > But if there are concurrent translation faults on the same page or block, > > clean of dcache for the first time is necessary while the others are not. > > > > By moving clean of dcache to the map handler, we can easily identify the > > conditions where CMOs are really needed and avoid the unnecessary ones. > > As it's a time consuming process to perform CMOs especially when flushing > > a block range, so this solution reduces much load of kvm and improve the > > efficiency of creating mappings. > > > > Signed-off-by: Yanan Wang > > --- > > arch/arm64/include/asm/kvm_mmu.h | 16 -------------- > > arch/arm64/kvm/hyp/pgtable.c | 38 ++++++++++++++++++++------------ > > arch/arm64/kvm/mmu.c | 14 +++--------- > > 3 files changed, 27 insertions(+), 41 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > > index e52d82aeadca..4ec9879e82ed 100644 > > --- a/arch/arm64/include/asm/kvm_mmu.h > > +++ b/arch/arm64/include/asm/kvm_mmu.h > > @@ -204,22 +204,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > > } > > > > -static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) > > -{ > > - void *va = page_address(pfn_to_page(pfn)); > > - > > - /* > > - * With FWB, we ensure that the guest always accesses memory using > > - * cacheable attributes, and we don't have to clean to PoC when > > - * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > - * PoU is not required either in this case. > > - */ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > - return; > > - > > - kvm_flush_dcache_to_poc(va, size); > > -} > > - > > static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > > unsigned long size) > > { > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index 4d177ce1d536..2f4f87021980 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -464,6 +464,26 @@ static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, > > return 0; > > } > > > > +static bool stage2_pte_cacheable(kvm_pte_t pte) > > +{ > > + u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > > + return memattr == PAGE_S2_MEMATTR(NORMAL); > > +} > > + > > +static void stage2_flush_dcache(void *addr, u64 size) > > +{ > > + /* > > + * With FWB, we ensure that the guest always accesses memory using > > + * cacheable attributes, and we don't have to clean to PoC when > > + * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > + * PoU is not required either in this case. > > + */ > > + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > + return; > > + > > + __flush_dcache_area(addr, size); > > +} > > + > > static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > kvm_pte_t *ptep, > > struct stage2_map_data *data) > > @@ -495,6 +515,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > put_page(page); > > } > > > > + /* Flush data cache before installation of the new PTE */ > > + if (stage2_pte_cacheable(new)) > > + stage2_flush_dcache(__va(phys), granule); > > This makes sense to me. kvm_pgtable_stage2_map() is protected > against concurrent calls by the kvm->mmu_lock, so only one VCPU can > change the stage 2 translation table at any given moment. In the > case of concurrent translation faults on the same IPA, the first > VCPU that will take the lock will create the mapping and do the > dcache clean+invalidate. The other VCPUs will return -EAGAIN because > the mapping they are trying to install is almost identical* to the > mapping created by the first VCPU that took the lock. > > I have a question. Why are you doing the cache maintenance *before* > installing the new mapping? This is what the kernel already does, so > I'm not saying it's incorrect, I'm just curious about the reason > behind it. The guarantee KVM offers to the guest is that by the time it can access the memory, it is cleaned to the PoC. If you establish a mapping before cleaning, another vcpu can access the PoC (no fault, you just set up S2) and not see it up to date. Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 437CEC433DB for ; Wed, 24 Feb 2021 17:39:52 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 7DED564F17 for ; Wed, 24 Feb 2021 17:39:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7DED564F17 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E0F4F4B20E; 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Wed, 24 Feb 2021 17:39:44 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lEy8U-00FjYK-CF; Wed, 24 Feb 2021 17:39:42 +0000 Date: Wed, 24 Feb 2021 17:39:41 +0000 Message-ID: <8735xl1i1u.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [RFC PATCH 1/4] KVM: arm64: Move the clean of dcache to the map handler In-Reply-To: <70b2d6c2-709b-d63b-1409-b16dad89b9b6@arm.com> References: <20210208112250.163568-1-wangyanan55@huawei.com> <20210208112250.163568-2-wangyanan55@huawei.com> <70b2d6c2-709b-d63b-1409-b16dad89b9b6@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, wangyanan55@huawei.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, gshan@redhat.com, qperret@google.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon , kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, 24 Feb 2021 17:21:22 +0000, Alexandru Elisei wrote: > > Hello, > > On 2/8/21 11:22 AM, Yanan Wang wrote: > > We currently uniformly clean dcache in user_mem_abort() before calling the > > fault handlers, if we take a translation fault and the pfn is cacheable. > > But if there are concurrent translation faults on the same page or block, > > clean of dcache for the first time is necessary while the others are not. > > > > By moving clean of dcache to the map handler, we can easily identify the > > conditions where CMOs are really needed and avoid the unnecessary ones. > > As it's a time consuming process to perform CMOs especially when flushing > > a block range, so this solution reduces much load of kvm and improve the > > efficiency of creating mappings. > > > > Signed-off-by: Yanan Wang > > --- > > arch/arm64/include/asm/kvm_mmu.h | 16 -------------- > > arch/arm64/kvm/hyp/pgtable.c | 38 ++++++++++++++++++++------------ > > arch/arm64/kvm/mmu.c | 14 +++--------- > > 3 files changed, 27 insertions(+), 41 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > > index e52d82aeadca..4ec9879e82ed 100644 > > --- a/arch/arm64/include/asm/kvm_mmu.h > > +++ b/arch/arm64/include/asm/kvm_mmu.h > > @@ -204,22 +204,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > > } > > > > -static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) > > -{ > > - void *va = page_address(pfn_to_page(pfn)); > > - > > - /* > > - * With FWB, we ensure that the guest always accesses memory using > > - * cacheable attributes, and we don't have to clean to PoC when > > - * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > - * PoU is not required either in this case. > > - */ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > - return; > > - > > - kvm_flush_dcache_to_poc(va, size); > > -} > > - > > static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > > unsigned long size) > > { > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index 4d177ce1d536..2f4f87021980 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -464,6 +464,26 @@ static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, > > return 0; > > } > > > > +static bool stage2_pte_cacheable(kvm_pte_t pte) > > +{ > > + u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > > + return memattr == PAGE_S2_MEMATTR(NORMAL); > > +} > > + > > +static void stage2_flush_dcache(void *addr, u64 size) > > +{ > > + /* > > + * With FWB, we ensure that the guest always accesses memory using > > + * cacheable attributes, and we don't have to clean to PoC when > > + * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > + * PoU is not required either in this case. > > + */ > > + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > + return; > > + > > + __flush_dcache_area(addr, size); > > +} > > + > > static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > kvm_pte_t *ptep, > > struct stage2_map_data *data) > > @@ -495,6 +515,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > put_page(page); > > } > > > > + /* Flush data cache before installation of the new PTE */ > > + if (stage2_pte_cacheable(new)) > > + stage2_flush_dcache(__va(phys), granule); > > This makes sense to me. kvm_pgtable_stage2_map() is protected > against concurrent calls by the kvm->mmu_lock, so only one VCPU can > change the stage 2 translation table at any given moment. In the > case of concurrent translation faults on the same IPA, the first > VCPU that will take the lock will create the mapping and do the > dcache clean+invalidate. The other VCPUs will return -EAGAIN because > the mapping they are trying to install is almost identical* to the > mapping created by the first VCPU that took the lock. > > I have a question. Why are you doing the cache maintenance *before* > installing the new mapping? This is what the kernel already does, so > I'm not saying it's incorrect, I'm just curious about the reason > behind it. The guarantee KVM offers to the guest is that by the time it can access the memory, it is cleaned to the PoC. If you establish a mapping before cleaning, another vcpu can access the PoC (no fault, you just set up S2) and not see it up to date. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3B5BC433E0 for ; Wed, 24 Feb 2021 17:41:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7260964E90 for ; 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SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210224_123945_962593_2A59C93F X-CRM114-Status: GOOD ( 36.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gavin Shan , kvm@vger.kernel.org, Suzuki K Poulose , Catalin Marinas , Quentin Perret , linux-kernel@vger.kernel.org, Yanan Wang , James Morse , linux-arm-kernel@lists.infradead.org, Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 24 Feb 2021 17:21:22 +0000, Alexandru Elisei wrote: > > Hello, > > On 2/8/21 11:22 AM, Yanan Wang wrote: > > We currently uniformly clean dcache in user_mem_abort() before calling the > > fault handlers, if we take a translation fault and the pfn is cacheable. > > But if there are concurrent translation faults on the same page or block, > > clean of dcache for the first time is necessary while the others are not. > > > > By moving clean of dcache to the map handler, we can easily identify the > > conditions where CMOs are really needed and avoid the unnecessary ones. > > As it's a time consuming process to perform CMOs especially when flushing > > a block range, so this solution reduces much load of kvm and improve the > > efficiency of creating mappings. > > > > Signed-off-by: Yanan Wang > > --- > > arch/arm64/include/asm/kvm_mmu.h | 16 -------------- > > arch/arm64/kvm/hyp/pgtable.c | 38 ++++++++++++++++++++------------ > > arch/arm64/kvm/mmu.c | 14 +++--------- > > 3 files changed, 27 insertions(+), 41 deletions(-) > > > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > > index e52d82aeadca..4ec9879e82ed 100644 > > --- a/arch/arm64/include/asm/kvm_mmu.h > > +++ b/arch/arm64/include/asm/kvm_mmu.h > > @@ -204,22 +204,6 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > > return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > > } > > > > -static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size) > > -{ > > - void *va = page_address(pfn_to_page(pfn)); > > - > > - /* > > - * With FWB, we ensure that the guest always accesses memory using > > - * cacheable attributes, and we don't have to clean to PoC when > > - * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > - * PoU is not required either in this case. > > - */ > > - if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > - return; > > - > > - kvm_flush_dcache_to_poc(va, size); > > -} > > - > > static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, > > unsigned long size) > > { > > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c > > index 4d177ce1d536..2f4f87021980 100644 > > --- a/arch/arm64/kvm/hyp/pgtable.c > > +++ b/arch/arm64/kvm/hyp/pgtable.c > > @@ -464,6 +464,26 @@ static int stage2_map_set_prot_attr(enum kvm_pgtable_prot prot, > > return 0; > > } > > > > +static bool stage2_pte_cacheable(kvm_pte_t pte) > > +{ > > + u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR; > > + return memattr == PAGE_S2_MEMATTR(NORMAL); > > +} > > + > > +static void stage2_flush_dcache(void *addr, u64 size) > > +{ > > + /* > > + * With FWB, we ensure that the guest always accesses memory using > > + * cacheable attributes, and we don't have to clean to PoC when > > + * faulting in pages. Furthermore, FWB implies IDC, so cleaning to > > + * PoU is not required either in this case. > > + */ > > + if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) > > + return; > > + > > + __flush_dcache_area(addr, size); > > +} > > + > > static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > kvm_pte_t *ptep, > > struct stage2_map_data *data) > > @@ -495,6 +515,10 @@ static int stage2_map_walker_try_leaf(u64 addr, u64 end, u32 level, > > put_page(page); > > } > > > > + /* Flush data cache before installation of the new PTE */ > > + if (stage2_pte_cacheable(new)) > > + stage2_flush_dcache(__va(phys), granule); > > This makes sense to me. kvm_pgtable_stage2_map() is protected > against concurrent calls by the kvm->mmu_lock, so only one VCPU can > change the stage 2 translation table at any given moment. In the > case of concurrent translation faults on the same IPA, the first > VCPU that will take the lock will create the mapping and do the > dcache clean+invalidate. The other VCPUs will return -EAGAIN because > the mapping they are trying to install is almost identical* to the > mapping created by the first VCPU that took the lock. > > I have a question. Why are you doing the cache maintenance *before* > installing the new mapping? This is what the kernel already does, so > I'm not saying it's incorrect, I'm just curious about the reason > behind it. The guarantee KVM offers to the guest is that by the time it can access the memory, it is cleaned to the PoC. If you establish a mapping before cleaning, another vcpu can access the PoC (no fault, you just set up S2) and not see it up to date. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel