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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20181123144558.5048-2-richard.henderson@linaro.org>
Date: Thu, 29 Nov 2018 12:52:13 +0000
Message-ID: <8736rk3v2a.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH for-4.0 v2 01/37] tcg/i386: Always use %ebp
 for TCG_AREG0
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To: qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com


Richard Henderson <richard.henderson@linaro.org> writes:

> For x86_64, this can result in smaller code when manipulating
> TCG_TYPE_I32, as we can omit a REX prefix.

I take it you mean passing TCG_TYPE_I32 back and forth from the register
backing store in CPUEnv which TCG_AREG0 points at?

Anyway:

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>


>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/i386/tcg-target.h | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 9fdf37f23c..7488c3d869 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -84,6 +84,8 @@ typedef enum {
>      TCG_REG_RBP =3D TCG_REG_EBP,
>      TCG_REG_RSI =3D TCG_REG_ESI,
>      TCG_REG_RDI =3D TCG_REG_EDI,
> +
> +    TCG_AREG0 =3D TCG_REG_EBP,
>  } TCGReg;
>
>  /* used for function call generation */
> @@ -194,12 +196,6 @@ extern bool have_avx2;
>  #define TCG_TARGET_extract_i64_valid(ofs, len) \
>      (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32)
>
> -#if TCG_TARGET_REG_BITS =3D=3D 64
> -# define TCG_AREG0 TCG_REG_R14
> -#else
> -# define TCG_AREG0 TCG_REG_EBP
> -#endif
> -
>  static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
>  {
>  }


--
Alex Benn=C3=A9e