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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
	benh@kernel.crashing.org,
	Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction
Date: Thu, 15 Sep 2016 12:10:45 +0530	[thread overview]
Message-ID: <8737l1zmvm.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> (raw)
In-Reply-To: <20160915010735.GI15077@voom.fritz.box>

David Gibson <david@gibson.dropbear.id.au> writes:

> [ Unknown signature status ]
> On Mon, Sep 12, 2016 at 12:11:40PM +0530, Nikunj A Dadhania wrote:
>> From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
>> 
>> darn: Deliver A Random Number
>> 
>> Currently return invalid random number for all the case. This needs
>> proper algorithm to provide cryptographically suitable random data.
>> Reading from /dev/random can block and that is not an expected behaviour
>> while the cpu instruction is getting executed. Moreover, /dev/random
>> would only work for linux-user
>> 
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>>  target-ppc/helper.h     |  2 ++
>>  target-ppc/int_helper.c | 16 ++++++++++++++++
>>  target-ppc/translate.c  | 18 ++++++++++++++++++
>>  3 files changed, 36 insertions(+)
>> 
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index e75d070..966f2ce 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -50,6 +50,8 @@ DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl)
>>  DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
>>  DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
>>  DEF_HELPER_3(srad, tl, env, tl, tl)
>> +DEF_HELPER_0(darn32, tl)
>> +DEF_HELPER_0(darn64, tl)
>>  #endif
>>  
>>  DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)
>> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> index 291fba0..51a9ac5 100644
>> --- a/target-ppc/int_helper.c
>> +++ b/target-ppc/int_helper.c
>> @@ -182,6 +182,22 @@ target_ulong helper_cnttzd(target_ulong t)
>>  {
>>      return ctz64(t);
>>  }
>> +
>> +/* Return invalid random number.
>> + *
>> + * FIXME: Add rng backend or other mechanism to get cryptographically suitable
>> + * random number
>> + */
>> +target_ulong helper_darn32(void)
>> +{
>> +    return -1;
>> +}
>> +
>> +target_ulong helper_darn64(void)
>> +{
>> +    return -1;
>> +}
>> +
>
> TBH, I think you're going to want a single helper for both 32-bit and
> 64-bit cases.

Initially, we used to split 32/64-bit in helper, Richard suggested to
make that decision in translate.c

>
>>  #endif
>>  
>>  #if defined(TARGET_PPC64)
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index 133c531..e9dad3f 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -528,6 +528,8 @@ EXTRACT_HELPER(FPW, 16, 1);
>>  
>>  /* addpcis */
>>  EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
>> +/* darn */
>> +EXTRACT_HELPER(L, 16, 2);
>>  
>>  /***                            Jump target decoding                       ***/
>>  /* Immediate address */
>> @@ -1895,6 +1897,21 @@ static void gen_cnttzd(DisasContext *ctx)
>>          gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
>>      }
>>  }
>> +
>> +/* darn */
>> +static void gen_darn(DisasContext *ctx)
>> +{
>> +    int l = L(ctx->opcode);
>> +
>> +    if (l == 0) {
>> +        gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
>> +    } else if (l <= 2) {
>> +        /* Return 64-bit random for both CRN and RRN */
>> +        gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
>
> So it might be simpler to just leave out the helper stubs for now, and
> always return the invalid value from the generated code.

The idea was to retain all the translation work that we did as stubs.
And fill it whenever we have suitable implementation. Wouldn't hurt to
leave it like this. I am fine both ways.

Regards,
Nikunj

  reply	other threads:[~2016-09-15  6:40 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-12  6:41 [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4 Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 01/17] target-ppc: consolidate load operations Nikunj A Dadhania
2016-09-15  0:46   ` David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur " Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r " Nikunj A Dadhania
2016-09-15  0:48   ` David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 07/17] target-ppc: consolidate load with reservation Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction Nikunj A Dadhania
2016-09-15  1:07   ` David Gibson
2016-09-15  6:40     ` Nikunj A Dadhania [this message]
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 12/17] target-ppc: add lxsi[bw]zx instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 14/17] target-ppc: improve lxvw4x implementation Nikunj A Dadhania
2016-09-15  1:20   ` David Gibson
2016-09-15  9:57     ` Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 15/17] target-ppc: add lxvb16x and lxvh8x Nikunj A Dadhania
2016-09-15  1:41   ` David Gibson
2016-09-16  8:26     ` Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation Nikunj A Dadhania
2016-09-15  1:44   ` David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x Nikunj A Dadhania
2016-09-15  1:46   ` David Gibson
2016-09-16  8:28     ` Nikunj A Dadhania
2016-09-12  7:19 ` [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4 no-reply
2016-09-15  0:56 ` David Gibson
2016-09-15  1:49   ` David Gibson

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