From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zk60F-00058H-3U for qemu-devel@nongnu.org; Thu, 08 Oct 2015 03:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zk60A-0007qQ-3G for qemu-devel@nongnu.org; Thu, 08 Oct 2015 03:52:39 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:35181) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zk609-0007qL-TU for qemu-devel@nongnu.org; Thu, 08 Oct 2015 03:52:34 -0400 Received: by wicge5 with SMTP id ge5so13241709wic.0 for ; Thu, 08 Oct 2015 00:52:33 -0700 (PDT) References: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> <1443911939-2825-2-git-send-email-edgar.iglesias@gmail.com> <87bncayjzn.fsf@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Thu, 08 Oct 2015 08:52:31 +0100 Message-ID: <8737xlyeyo.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Edgar Iglesias , QEMU Developers , Alexander Graf , Sergey Fedorov , Laurent Desnogues , "Edgar E. Iglesias" Peter Maydell writes: > On 7 October 2015 at 12:51, Alex Bennée wrote: >> >> Edgar E. Iglesias writes: >> >>> From: "Edgar E. Iglesias" >>> >>> Signed-off-by: Edgar E. Iglesias >>> --- >>> target-arm/cpu.h | 1 + >>> target-arm/helper.c | 12 ++++++++++++ >>> 2 files changed, 13 insertions(+) >>> >>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >>> index cc1578c..895f2c2 100644 >>> --- a/target-arm/cpu.h >>> +++ b/target-arm/cpu.h >>> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >>> }; >>> uint64_t far_el[4]; >>> }; >>> + uint64_t hpfar_el2; >>> union { /* Translation result. */ >>> struct { >>> uint64_t _unused_par_0; >>> diff --git a/target-arm/helper.c b/target-arm/helper.c >>> index 8367997..5a5e5f0 100644 >>> --- a/target-arm/helper.c >>> +++ b/target-arm/helper.c >>> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >>> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >>> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >>> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >>> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >>> + .type = ARM_CP_CONST, .resetvalue = 0 }, >> >> So what happens if access_el3_aa32ns_aa64any thinks it is OK to access >> the register from EL3 when there is no EL2? What ensures we get RES0? > > ...the fact we've defined it as an RW CONST register with a resetvalue > of zero? Or am I misunderstanding your question? Nope you didn't misunderstand, I was being dim comparing with the later definitions ;-) Thanks. > > thanks > -- PMM -- Alex Bennée