From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751338AbaJAJp4 (ORCPT ); Wed, 1 Oct 2014 05:45:56 -0400 Received: from e28smtp09.in.ibm.com ([122.248.162.9]:58590 "EHLO e28smtp09.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751053AbaJAJpy (ORCPT ); Wed, 1 Oct 2014 05:45:54 -0400 From: "Aneesh Kumar K.V" To: Michael Neuling , greg@kroah.com, arnd@arndb.de, mpe@ellerman.id.au, benh@kernel.crashing.org Cc: mikey@neuling.org, anton@samba.org, linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, jk@ozlabs.org, imunsie@au1.ibm.com, cbe-oss-dev@lists.ozlabs.org Subject: Re: [PATCH v2 02/17] powerpc/cell: Move data segment faulting code out of cell platform In-Reply-To: <1412073306-13812-3-git-send-email-mikey@neuling.org> References: <1412073306-13812-1-git-send-email-mikey@neuling.org> <1412073306-13812-3-git-send-email-mikey@neuling.org> User-Agent: Notmuch/0.18.1 (http://notmuchmail.org) Emacs/24.3.91.1 (x86_64-unknown-linux-gnu) Date: Wed, 01 Oct 2014 15:15:40 +0530 Message-ID: <8738b8nmwr.fsf@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14100109-2674-0000-0000-000002131D5C Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Michael Neuling writes: > From: Ian Munsie > > __spu_trap_data_seg() currently contains code to determine the VSID and ESID > required for a particular EA and mm struct. > > This code is generically useful for other co-processors. This moves the code > of the cell platform so it can be used by other powerpc code. It also adds 1TB > segment handling which Cell didn't have. > > Signed-off-by: Ian Munsie > Signed-off-by: Michael Neuling > --- > arch/powerpc/include/asm/mmu-hash64.h | 7 ++++- > arch/powerpc/mm/copro_fault.c | 48 ++++++++++++++++++++++++++++++++++ > arch/powerpc/mm/slb.c | 3 --- > arch/powerpc/platforms/cell/spu_base.c | 41 +++-------------------------- > 4 files changed, 58 insertions(+), 41 deletions(-) > > diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h > index d765144..6d0b7a2 100644 > --- a/arch/powerpc/include/asm/mmu-hash64.h > +++ b/arch/powerpc/include/asm/mmu-hash64.h > @@ -189,7 +189,12 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) > #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) > > #ifndef __ASSEMBLY__ > - > +static inline int slb_vsid_shift(int ssize) > +{ > + if (ssize == MMU_SEGSIZE_256M) > + return SLB_VSID_SHIFT; > + return SLB_VSID_SHIFT_1T; > +} > static inline int segment_shift(int ssize) > { > if (ssize == MMU_SEGSIZE_256M) > diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c > index ba7df14..b865697 100644 > --- a/arch/powerpc/mm/copro_fault.c > +++ b/arch/powerpc/mm/copro_fault.c > @@ -90,3 +90,51 @@ out_unlock: > return ret; > } > EXPORT_SYMBOL_GPL(copro_handle_mm_fault); > + > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid) > +{ > + int psize, ssize; > + > + *esid = (ea & ESID_MASK) | SLB_ESID_V; > + > + switch (REGION_ID(ea)) { > + case USER_REGION_ID: > + pr_devel("copro_data_segment: 0x%llx -- USER_REGION_ID\n", ea); > +#ifdef CONFIG_PPC_MM_SLICES > + psize = get_slice_psize(mm, ea); > +#else > + psize = mm->context.user_psize; > +#endif We don't really need that as explained in last review. -aneesh From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id DF2AD1A1777 for ; Wed, 1 Oct 2014 19:46:03 +1000 (EST) Received: from e28smtp05.in.ibm.com (e28smtp05.in.ibm.com [122.248.162.5]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5CF0E140140 for ; Wed, 1 Oct 2014 19:46:01 +1000 (EST) Received: from /spool/local by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 1 Oct 2014 15:15:57 +0530 From: "Aneesh Kumar K.V" To: Michael Neuling , greg@kroah.com, arnd@arndb.de, mpe@ellerman.id.au, benh@kernel.crashing.org Subject: Re: [PATCH v2 02/17] powerpc/cell: Move data segment faulting code out of cell platform In-Reply-To: <1412073306-13812-3-git-send-email-mikey@neuling.org> References: <1412073306-13812-1-git-send-email-mikey@neuling.org> <1412073306-13812-3-git-send-email-mikey@neuling.org> Date: Wed, 01 Oct 2014 15:15:40 +0530 Message-ID: <8738b8nmwr.fsf@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain Cc: cbe-oss-dev@lists.ozlabs.org, mikey@neuling.org, linux-kernel@vger.kernel.org, linuxppc-dev@ozlabs.org, jk@ozlabs.org, imunsie@au1.ibm.com, anton@samba.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Michael Neuling writes: > From: Ian Munsie > > __spu_trap_data_seg() currently contains code to determine the VSID and ESID > required for a particular EA and mm struct. > > This code is generically useful for other co-processors. This moves the code > of the cell platform so it can be used by other powerpc code. It also adds 1TB > segment handling which Cell didn't have. > > Signed-off-by: Ian Munsie > Signed-off-by: Michael Neuling > --- > arch/powerpc/include/asm/mmu-hash64.h | 7 ++++- > arch/powerpc/mm/copro_fault.c | 48 ++++++++++++++++++++++++++++++++++ > arch/powerpc/mm/slb.c | 3 --- > arch/powerpc/platforms/cell/spu_base.c | 41 +++-------------------------- > 4 files changed, 58 insertions(+), 41 deletions(-) > > diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h > index d765144..6d0b7a2 100644 > --- a/arch/powerpc/include/asm/mmu-hash64.h > +++ b/arch/powerpc/include/asm/mmu-hash64.h > @@ -189,7 +189,12 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) > #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) > > #ifndef __ASSEMBLY__ > - > +static inline int slb_vsid_shift(int ssize) > +{ > + if (ssize == MMU_SEGSIZE_256M) > + return SLB_VSID_SHIFT; > + return SLB_VSID_SHIFT_1T; > +} > static inline int segment_shift(int ssize) > { > if (ssize == MMU_SEGSIZE_256M) > diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c > index ba7df14..b865697 100644 > --- a/arch/powerpc/mm/copro_fault.c > +++ b/arch/powerpc/mm/copro_fault.c > @@ -90,3 +90,51 @@ out_unlock: > return ret; > } > EXPORT_SYMBOL_GPL(copro_handle_mm_fault); > + > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid) > +{ > + int psize, ssize; > + > + *esid = (ea & ESID_MASK) | SLB_ESID_V; > + > + switch (REGION_ID(ea)) { > + case USER_REGION_ID: > + pr_devel("copro_data_segment: 0x%llx -- USER_REGION_ID\n", ea); > +#ifdef CONFIG_PPC_MM_SLICES > + psize = get_slice_psize(mm, ea); > +#else > + psize = mm->context.user_psize; > +#endif We don't really need that as explained in last review. -aneesh