From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bywco-0008TV-67 for qemu-devel@nongnu.org; Tue, 25 Oct 2016 03:58:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bywcj-0006MP-CG for qemu-devel@nongnu.org; Tue, 25 Oct 2016 03:58:22 -0400 Received: from 5.mo68.mail-out.ovh.net ([46.105.62.179]:51508) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bywcj-0006M1-5y for qemu-devel@nongnu.org; Tue, 25 Oct 2016 03:58:17 -0400 Received: from player788.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 615149654 for ; Tue, 25 Oct 2016 09:58:15 +0200 (CEST) References: <1477129610-31353-1-git-send-email-clg@kaod.org> <1477129610-31353-16-git-send-email-clg@kaod.org> <20161025053007.GA11052@umbus.fritz.box> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <87421643-0697-40d3-8c28-d00348c0c54d@kaod.org> Date: Tue, 25 Oct 2016 09:58:10 +0200 MIME-Version: 1.0 In-Reply-To: <20161025053007.GA11052@umbus.fritz.box> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf On 10/25/2016 07:30 AM, David Gibson wrote: > On Sat, Oct 22, 2016 at 11:46:48AM +0200, C=E9dric Le Goater wrote: >> From: Benjamin Herrenschmidt >> >> The PSI (Processor Service Interface) is one of the engines of the >> "Bridge" unit which connects the different interfaces to the Power >> Processor. >> >> This adds just enough of the PSI bridge to handle various on-chip and >> the one external interrupt. The rest of PSI has to do with the link to >> the IBM FSP service processor which we don't plan to emulate (not used >> on OpenPower machines). >> >> Signed-off-by: Benjamin Herrenschmidt >> [clg: - updated for qemu-2.7 >> - changed the XSCOM interface to fit new model >> - QOMified the model >> - reworked set_xive ] >> Signed-off-by: C=E9dric Le Goater >> --- >> >> When skiboot initializes PSIHB, it fills the xives with server=3D0, >> prio=3D0xff, which is fine, but for some reason the last two xive >> settings reach the qemu MMIO region with a bogus value : >> =20 >> pnv_psi_mmio_write: MMIO write 0x30 val 0x000000ff00000000 >> pnv_psi_mmio_write: MMIO write 0x60 val 0x000000ff20000000 >> pnv_psi_mmio_write: MMIO write 0x68 val 0x000000ff40000000 >> pnv_psi_mmio_write: MMIO write 0x70 val 0x000000ff60000000 >> pnv_psi_mmio_write: MMIO write 0x78 val 0xffffffff80000000 >> pnv_psi_mmio_write: MMIO write 0x80 val 0xffffffffa0000000 >> >> It looks like a badly initialized temp variable in the call >> stack. The memory regions look fine, maybe in stdcix ? For the >> moment, I have added a logging error to catch non zero values as the >> guest should not do that in any case. >=20 > Just to clarify, I think you're saying that you believe this to be a > skiboot (guest side) bug rather than a qemu bug. Is that right? Yes. I just found why. The P8_IRQ_PSI_* values in skiboot need to be unsigned because they are shifted left of 29 bits : ... #define P8_IRQ_PSI_LOCAL_ERR 4 #define P8_IRQ_PSI_EXTERNAL 5 /* Used for UART */ ... out_be64(psi->regs + PSIHB_XIVR_LOCAL_ERR, (0xffull << 32) | (P8_IRQ_PSI_LOCAL_ERR << 29)); out_be64(psi->regs + PSIHB_XIVR_HOST_ERR, (0xffull << 32) | (P8_IRQ_PSI_EXTERNAL << 29)); I will send a skiboot patch but we need to keep the code as it is.=20 Thanks C.=20 =20